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Travelled to:
3 × USA
Collaborated with:
A.E.Gamal M.A.Breuer H.W.Carter
Talks about:
rout (2) steinberg (1) placement (1) increment (1) procedur (1) statist (1) process (1) circuit (1) integr (1) custom (1)

Person: Zahir A. Syed

DBLP DBLP: Syed:Zahir_A=

Contributed to:

DAC 19831983
DAC 19821982
DAC 19791979

Wrote 3 papers:

DAC-1983-GamalS #array #statistics
A new statistical model for gate array routing (AEG, ZAS), pp. 671–674.
DAC-1982-SyedGB #on the
On routing for custom integrated circuits (ZAS, AEG, MAB), pp. 887–893.
DAC-1979-CarterBS #incremental
Incremental processing applied to Steinberg’s placement procedure (HWC, MAB, ZAS), pp. 26–31.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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