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Travelled to:
1 × China
1 × France
1 × Germany
1 × USA
Collaborated with:
X.S.Hu J.Zhu M.Kirkpatrick E.H.Sha Z.Chi C.Wang
Talks about:
schedul (2) partit (2) memori (2) level (2) architectur (1) transistor (1) waveform (1) piecewis (1) instruct (1) variabl (1)

Person: Zhong Wang

DBLP DBLP: Wang:Zhong

Contributed to:

DATE v1 20042004
DATE 20032003
DAC 20002000
TOOLS Asia 19991999

Wrote 4 papers:

DATE-v1-2004-WangH #clustering #memory management #multi #power management #scheduling
Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks (ZW, XSH), pp. 312–317.
DATE-2003-WangZ #analysis #polynomial
Transistor-Level Static Timing Analysis by Piecewise Quadratic Waveform Matching (ZW, JZ), pp. 11026–11031.
DAC-2000-WangKS #clustering #latency #memory management #scheduling
Optimal two level partitioning and loop scheduling for hiding memory latency for DSP applications (ZW, MK, EHMS), pp. 540–545.
TOOLS-ASIA-1999-WangCW #adaptation #architecture #component #multi #named #reuse
MAC: A Component Reuse Architecture Based on Multi-Agent Adapter (ZW, ZC, CW), pp. 267–272.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.