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architectur (4)
power (4)
low (4)
processor (4)
level (4)

Stem baseband$ (all stems)

14 papers:

DATEDATE-2014-TangZS #design #development #performance
System-level design methodology enabling fast development of baseband MP-SoC for 4G small cell base station (ST, ZZ, YS), pp. 1–6.
Configurability in IP subystems: baseband examples (PXT, GM, DH, DM, JK), pp. 163–168.
DATEDATE-2013-ZhuTSHSS #communication
A 100 GOPS ASP based baseband processor for wireless communication (ZZ, ST, YS, JH, GS, JS), pp. 121–124.
DATEDATE-2010-RaabBHLSESE #design #power management
Low power design of the X-GOLD® SDR 20 baseband processor (WR, JB, JAUH, DL, MS, HE, JUS, GE), pp. 792–793.
DATEDATE-2009-AlimohammadFC #algorithm #architecture #development #flexibility #verification
A flexible layered architecture for accurate digital baseband algorithm development and verification (AA, SFF, BFC), pp. 45–50.
DATEDATE-2009-BachmannGHBS #power management
A low-power ASIP for IEEE 802.15.4a ultra-wideband impulse radio baseband processing (CB, AG, JH, MB, CS), pp. 1614–1619.
DACDAC-2008-LiBNPC #approach #how #implementation #power management #set
How to let instruction set processor beat ASIC for low power wireless baseband implementation: a system level approach (ML, BB, DN, LVdP, FC), pp. 345–346.
DATEDATE-2008-BougardSRNADP #array
A Coarse-Grained Array based Baseband Processor for 100Mbps+ Software Defined Radio (BB, BDS, SR, DN, OA, SD, LVdP), pp. 716–721.
DATEDATE-2008-LiBXNPC #architecture #detection #optimisation #parallel #programmable
Optimizing Near-ML MIMO Detector for SDR Baseband on Parallel Programmable Architectures (ML, BB, WX, DN, LVdP, FC), pp. 444–449.
DATEDATE-2008-LiNBPC #architecture #multi
Generic Multi-Phase Software-Pipelined Partial-FFT on Instruction-Level-Parallel Architectures and SDR Baseband Applications (ML, DN, BB, LVdP, FC), pp. 598–603.
DATEDATE-2007-SchamannHLB #algorithm #architecture #case study #design #power management
Low power design on algorithmic and architectural level: a case study of an HSDPA baseband digital signal processing system (MS, SH, UL, MB), pp. 1406–1411.
DACDAC-2003-MathysC #integration #verification
Verification strategy for integration 3G baseband SoC (YM, AC), pp. 7–10.
DACDAC-2001-GrahmC #integration #reuse
SoC Integration of Reusable Baseband Bluetooth IP (TG, BC), pp. 256–261.
Smart Antenna Receiver Based on a Single Chip Solution for GSM/DCS Baseband Processing (UG, AP, DV), pp. 181–185.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.