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Used together with:
system (5)
model (5)
no (3)
design (3)
asynchron (3)

Stem gal$ (all stems)

13 papers:

DATEDATE-2015-BurnsSY #modelling #synthesis #verification
GALS synthesis and verification for xMAS models (FPB, DS, AY), pp. 1419–1424.
FSEFSE-2014-JiangZZZLSSGS #embedded #modelling #multi #named #synthesis #tool support #validation
Tsmart-GalsBlock: a toolkit for modeling, validation, and synthesis of multi-clocked embedded systems (YJ, HZ, HZ, XZ, HL, CS, XS, MG, JGS), pp. 711–714.
DATEDATE-2013-GhiribaldiBN #architecture #effectiveness #manycore
A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systems (AG, DB, SMN), pp. 332–337.
DATEDATE-2013-YakovlevVR #industrial #logic #roadmap #tool support
Advances in asynchronous logic: from principles to GALS & NoC, recent industry applications, and commercial CAD tools (AY, PV, MR), pp. 1715–1724.
DATEDATE-2012-FanKGSH #design #integration
Exploring pausible clocking based GALS design for 40-nm system integration (XF, MK, EG, BS, CH), pp. 1118–1121.
DATEDATE-2010-LudoviciSGBB #design #effectiveness #flexibility
Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs (DL, AS, GNG, LB, DB), pp. 679–684.
DATEDATE-2010-ThonnartVC #framework #integration #power management
A fully-asynchronous low-power framework for GALS NoC integration (YT, PV, FC), pp. 33–38.
CAVCAV-2009-CosteHLS #composition #design #industrial #modelling #performance #predict #towards
Towards Performance Prediction of Compositional Models in Industrial GALS Designs (NC, HH, EL, WS), pp. 204–218.
DACDAC-2007-OgrasMCM #clustering
Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip (ÜYO, RM, PC, DM), pp. 110–115.
DATEDATE-2007-WatanabeKINN #constraints #energy #interactive #multi #performance #scheduling
Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC (RW, MK, MI, HN, TN), pp. 797–802.
DATEDATE-DF-2006-CampobelloCCM #network
GALS networks on chip: a new solution for asynchronous delay-insensitive links (GC, MC, CC, DM), pp. 160–165.
CAVCAV-2004-RameshSDCV #modelling #tool support #verification
A Toolset for Modelling and Verification of GALS Systems (SR, SS, VD, NC, BV), pp. 506–509.
SACSAC-2003-CheongLLZ #embedded #named #programming
TinyGALS: A Programming Model for Event-Driven Embedded Systems (EC, JL, JL, FZ), pp. 698–704.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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