25 papers:
DATE-2015-BombieriFPS #abstraction #verification- RTL property abstraction for TLM assertion-based verification (NB, RF, GP, FS), pp. 85–90.
SEFM-2014-HajisheykhiEK #fault #modelling #using- Evaluating the Effect of Faults in SystemC TLM Models Using UPPAAL (RH, AE, SSK), pp. 175–189.
- DATE-2013-BouhadibaMM #energy #modelling #validation
- System-level modeling of energy in TLM for early validation of power and thermal management (TB, MM, FM), pp. 1609–1614.
- DATE-2013-HelmstetterCGMV #performance #simulation #using
- Fast and accurate TLM simulations using temporal decoupling for FIFO-based communications (CH, JC, BG, MM, PV), pp. 1185–1188.
- DATE-2013-LeGD #design #fault #locality #scalability
- Scalable fault localization for SystemC TLM designs (HML, DG, RD), pp. 35–38.
- DATE-2011-GrammatikakisPSP #estimation #using
- System-level power estimation methodology using cycle- and bit-accurate TLM (MDG, SP, JPS, CP), pp. 1125–1126.
ECMFA-2011-JainKP #development #modelling #validation- A SysML Profile for Development and Early Validation of TLM 2.0 Models (VJ, AK, PRP), pp. 299–311.
- DATE-2010-BeckerGF0PX #design #refinement
- RTOS-aware refinement for TLM2.0-based HW/SW designs (MB, GDG, FF, WM, GP, TX), pp. 1053–1058.
- DATE-2010-EckerESSV #embedded #modelling
- TLM+ modeling of embedded HW/SW systems (WE, VE, RS, TS, MV), pp. 75–80.
- DATE-2010-MelloMGP #parallel #simulation
- Parallel simulation of systemC TLM 2.0 compliant MPSoC on SMP workstations (AM, IM, AG, FP), pp. 606–609.
- DATE-2010-SchulzBUES #modelling #transaction
- Transmitting TLM transactions over analogue wire models (SS, JB, TU, KE, SS), pp. 1608–1613.
- DATE-2010-WuLCT #abstraction #automation #generative #multi #performance
- Automatic generation of software TLM in multiple abstraction layers for efficient HW/SW co-simulation (MHW, WCL, CYC, RST), pp. 1177–1182.
- DATE-2009-BombieriFPHL #functional #verification
- Functional qualification of TLM verification (NB, FF, GP, MH, FL), pp. 190–195.
- DATE-2009-MollCRB #modelling #performance #protocol #using
- Fast and accurate protocol specific bus modeling using TLM 2.0 (HWMvM, HC, VR, MB), pp. 316–319.
DAC-2008-KunduGG #design #partial order #reduction #scalability #testing- Partial order reduction for scalable testing of systemC TLM designs (SK, MKG, RG), pp. 936–941.
- DATE-2008-BombieriDF #automation #design #generative
- Integrating RTL IPs into TLM Designs Through Automatic Transactor Generation (NB, ND, FF), pp. 15–20.
- DATE-2008-BombieriFP #communication #interface
- A Mutation Model for the SystemC TLM 2.0 Communication Interfaces (NB, FF, GP), pp. 396–401.
FM-2008-PonsiniS #modelling #semantics- A Schedulerless Semantics of TLM Models Written in SystemC Via Translation into LOTOS (OP, WS), pp. 278–293.
- DAC-2007-BacchiniGMKDMGN #named
- TLM: Crossing Over From Buzz To Adoption (FB, DDG, LMC, HK, JD, TM, JG, RSN), pp. 444–445.
- DAC-2007-KasuyaT #design #verification
- Verification Methodologies in a TLM-to-RTL Design Flow (AK, TT), pp. 199–204.
- DATE-2006-BeltrameSSLP #simulation
- Exploiting TLM and object introspection for system-level simulation (GB, DS, CS, DL, CP), pp. 100–105.
- DATE-2006-BombieriFP #evaluation #on the #reuse #verification
- On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL (NB, FF, GP), pp. 1007–1012.
- DATE-2006-HabibiTSLM #performance #using #verification
- Efficient assertion based verification using TLM (AH, ST, AS, DL, OAM), pp. 106–111.
- DATE-2006-KlingaufGG #architecture #named #transaction
- TRAIN: a virtual transaction layer architecture for TLM-based HW/SW codesign of synthesizable MPSoC (WK, HG, RG), pp. 1318–1323.
- DATE-2006-ViaudPG #modelling #parallel #performance #simulation
- An efficient TLM/T modeling and simulation environment based on conservative parallel discrete event principles (EV, FP, AG), pp. 94–99.
