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Travelled to:
2 × France
3 × Germany
5 × USA
Collaborated with:
R.K.Brayton A.L.Sangiovanni-Vincentelli M.Fujita S.M.Reddy G.R.Wilke Z.Wang J.S.Roychowdhury A.L.Oliveira T.Miyoshi T.Horie M.B.Tahoori Y.Nishizaki N.V.Shenoy W.Zhang Y.Zhu W.Yu L.Zhang R.Shi H.Peng Z.Zhu L.Chua-Eoan T.Shibuya N.Ito C.Cheng
Talks about:
synthesi (3) gate (3) base (3) substrat (2) programm (2) transit (2) power (2) clock (2) array (2) nois (2)

Person: Rajeev Murgai

DBLP DBLP: Murgai:Rajeev

Contributed to:

DATE 20082008
DATE 20062006
DATE v1 20042004
DATE v2 20042004
DATE 19991999
DAC 19981998
DAC 19941994
DAC 19931993
DAC 19921992
DAC 19901990

Wrote 10 papers:

DATE-2008-ZhangZYZSPZCMSIC #multi #network
Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network (WZ, YZ, WY, LZ, RS, HP, ZZ, LCE, RM, TS, NI, CKC), pp. 537–540.
DATE-2006-ReddyWM #architecture #nondeterminism
Analyzing timing uncertainty in mesh-based clock architectures (SMR, GRW, RM), pp. 1097–1102.
DATE-v1-2004-MurgaiRMHT #analysis #modelling
Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise Analysis (RM, SMR, TM, TH, MBT), pp. 610–615.
DATE-v2-2004-WangMR #automation #megamodelling #predict
Automated, Accurate Macromodelling of Digital Aggressors for Power/Ground/Substrate Noise Prediction (ZW, RM, JSR), pp. 824–829.
DATE-1999-MurgaiF #on the
On Reducing Transitions Through Data Modifications (RM, MF), p. 82–?.
DAC-1998-MurgaiFO #using
Using Complementation and Resequencing to Minimize Transitions (RM, MF, ALO), pp. 694–697.
DAC-1994-MurgaiBS #composition #encoding #functional #using
Optimum Functional Decomposition Using Encoding (RM, RKB, ALSV), pp. 408–414.
DAC-1993-MurgaiBS #array #programmable #synthesis
Sequential Synthesis for Table Look Up Programmable Gate Arrays (RM, RKB, ALSV), pp. 224–229.
DAC-1992-MurgaiBS #algorithm #multi #synthesis
An Improved Synthesis Algorithm for Multiplexor-Based PGA’s (RM, RKB, ALSV), pp. 380–386.
DAC-1990-MurgaiNSBS #array #logic #programmable #synthesis
Logic Synthesis for Programmable Gate Arrays (RM, YN, NVS, RKB, ALSV), pp. 620–625.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.