Travelled to:1 × France
1 × Germany
2 × USA
Collaborated with:H.Matsutani M.Koibuchi I.Fujiwara T.Yoshinaga J.M.Kühn D.Peterson O.Bringmann W.Rosenstiel H.Nishi K.Tasho J.Yamamoto T.Kudoh R.Kawano S.Tade T.Kagami Y.Take T.Kuroda P.Bogdan R.Marculescu M.Kondo H.Kobayashi R.Sakamoto M.Wada J.Tsukamoto M.Namiki W.Wang K.Matsunaga M.Kudo K.Usami T.Komoda H.Nakamura
Talks about:latenc (3) low (3) network (2) router (2) chip (2) no (2) microprocessor (1) architectur (1) wireless (1) shortcut (1)
Person: Hideharu Amano
DBLP: Amano:Hideharu
Contributed to:
2015
20152014
2009
2000Wrote 6 papers:
- DATE-2015-KuhnPABR
- Spatial and temporal granularity limits of body biasing in UTBB-FDSOI (JMK, DP, HA, OB, WR), pp. 876–879.
- PDP-2015-KawanoTFMAK
- Optimized Core-Links for Low-Latency NoCs (RK, ST, IF, HM, HA, MK), pp. 172–176.
- DATE-2014-KondoKSWTNWAMKUKN #design #embedded #evaluation #fine-grained
- Design and evaluation of fine-grained power-gating for embedded microprocessors (MK, HK, RS, MW, JT, MN, WW, HA, KM, MK, KU, TK, HN), pp. 1–6.
- DATE-2014-MatsutaniKFKTKBMA #3d #random
- Low-latency wireless 3D NoCs via randomized shortcut chips (HM, MK, IF, TK, YT, TK, PB, RM, HA), pp. 1–6.
- HPCA-2009-MatsutaniKAY #architecture #latency #predict
- Prediction router: Yet another low latency on-chip router architecture (HM, MK, HA, TY), pp. 367–378.
- HPDC-2000-NishiTYKA #network #parallel #performance
- A Local Area System Network RHinet-1: A Network for High Performance Parallel Computing (HN, KT, JY, TK, HA), pp. 296–297.