Stem router$ (all stems)

121 papers:

DAC-2015-HanKL #design #evaluation #using

Evaluation of BEOL design rule impacts using an optimal ILP-based detailed router (KH, ABK, HL), p. 6.

DATE-2015-MazloumiM #hybrid #memory management #multi

A hybrid packet/circuit-switched router to accelerate memory access in NoC-based chip multiprocessors (AM, MM), pp. 908–911.

HPCA-2015-ChenZPP #towards

Power punch: Towards non-blocking power-gating of NoC routers (LC, DZ, MP, TMP), pp. 378–389.

DATE-2014-JonnaJRM

Minimally buffered single-cycle deflection router (GRJ, JJ, RR, MM), pp. 1–4.

DATE-2014-SeitanidisPDN #architecture #named

ElastiStore: An elastic buffer architecture for Network-on-Chip routers (IS, AP, GD, CN), pp. 1–6.

ICALP-v2-2014-KosowskiP #case study #difference

Does Adding More Agents Make a Difference? A Case Study of Cover Time for the Rotor-Router (AK, DP), pp. 544–555.

ICEIS-v1-2014-CoelhoAABB #network #using

Router Nodes Positioning for Wireless Networks Using Artificial Immune Systems (PHGC, JLMdA, JFMdA, LFdAB, AVdB), pp. 415–421.

DAC-2013-AncajasNCR #architecture

HCI-tolerant NoC router microarchitecture (DMA, JMN, KC, SR), p. 10.

DAC-2013-HeHCKLCY #integration #quality

Ripple 2.0: high quality routability-driven placement via global router integration (XH, TH, WKC, JK, KCL, WC, EFYY), p. 6.

DATE-2013-DimitrakopoulosGNK #multi

Switch folding: network-on-chip routers with time-multiplexed output ports (GD, NG, CN, EK), pp. 344–349.

DATE-2013-JoseNKM #adaptation #named

DeBAR: deflection based adaptive router with minimal buffering (JJ, BN, DKK, MM), pp. 1583–1588.

SIGMOD-2013-VianaM #named #network #realtime #social

FriendRouter: real-time path finder in social networks (WV, MMM), pp. 1281–1282.

HPCA-2013-ChangHPNXK #named #network

TS-Router: On maximizing the Quality-of-Allocation in the On-Chip Network (YYC, YSCH, MP, VN, YX, CTK), pp. 390–399.

HPCA-2013-SamihWKMTS #energy

Energy-efficient interconnect via Router Parking (AS, RW, AK, CM, TYCT, YS), pp. 508–519.

DAC-2012-KahngLN #estimation #modelling

Explicit modeling of control and data for improved NoC router estimation (ABK, BL, SN), pp. 392–397.

DAC-2012-ZhangC #named

GDRouter: interleaved global routing and detailed routing for ultimate routability (YZ, CC), pp. 597–602.

DATE-2012-0002EGB #performance #using

Area efficient asynchronous SDM routers using 2-stage Clos switches (WS, DAE, JDG, WJB), pp. 1495–1500.

HPCA-2012-AhnCK #approach #architecture #network #scalability

Network within a network approach to create a scalable high-radix router microarchitecture (JHA, SC, JK), pp. 455–466.

DAC-2011-DingGYP #detection #learning #named

AENEID: a generic lithography-friendly detailed router based on post-RET data learning and hotspot detection (DD, JRG, KY, DZP), pp. 795–800.

DAC-2011-KimKY #named #network #power management

FlexiBuffer: reducing leakage power in on-chip network routers (GK, JK, SY), pp. 936–941.

PADL-2011-VoellmyH #named #network #programming

Nettle: Taking the Sting Out of Programming Network Routers (AV, PH), pp. 235–249.

HPCA-2011-FallinCM #named

CHIPPER: A low-complexity bufferless deflection router (CF, CC, OM), pp. 144–155.

DAC-2010-LiaoYB #performance

A new IP lookup cache for high performance IP routers (GL, HY, LNB), pp. 338–343.

HPCA-2010-XuZZY #throughput

Simple virtual channel allocation for high throughput and high frequency on-chip routers (YX, BZ, YZ, JY), pp. 1–11.

DAC-2009-DingZHCP #framework #integration #named #power management

O-Router: an optical routing framework for low power on-chip silicon nano-photonic integration (DD, YZ, HH, RTC, DZP), pp. 264–269.

DAC-2009-JangP

An SDRAM-aware router for Networks-on-Chip (WJ, DZP), pp. 800–805.

HPCA-2009-MatsutaniKAY #architecture #latency #predict

Prediction router: Yet another low latency on-chip router architecture (HM, MK, HA, TY), pp. 367–378.

SOSP-2009-DobrescuEACFIKMR #named #parallel

RouteBricks: exploiting parallelism to scale software routers (MD, NE, KJA, BGC, KRF, GI, AK, MM, SR), pp. 15–28.

DAC-2008-ChoYBP #named #performance #predict

ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction (MC, KY, YB, DZP), pp. 504–509.

DAC-2008-LaiWGLD #architecture

A dynamically-allocated virtual channel architecture with congestion awareness for on-chip routers (McL, ZW, LG, HL, KD), pp. 630–633.

DATE-2008-FaruqueH #architecture #communication

Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures (MAAF, JH), pp. 1238–1243.

DATE-2008-SammanHG #architecture #parallel #pipes and filters

Multicast Parallel Pipeline Router Architecture for Network-on-Chip (FAS, TH, MG), pp. 1396–1401.

DAC-2007-ChoXPP #named

TROY: Track Router with Yield-driven Wire Planning (MC, HX, RP, DZP), pp. 55–58.

DATE-2007-OgrasM #analysis #modelling #performance

Analytical router modeling for networks-on-chip performance analysis (ÜYO, RM), pp. 1096–1101.

DAC-2006-ChoP #named

BoxRouter: a new global router based on box expansion and progressive ILP (MC, DZP), pp. 373–378.

DATE-2006-SethuramanV #architecture #automation #generative #multi #named #using

optiMap: a tool for automated generation of noc architectures using multi-port routers for FPGAs (BS, RV), pp. 947–952.

SOFTVIS-2006-WendlandtCTM #network #visual notation #visualisation

The Clack graphical router: visualizing network software (DW, MC, PT, NM), pp. 7–15.

DAC-2005-KimPTVD #adaptation #latency

A low latency router supporting adaptivity for on-chip interconnects (JK, DP, TT, NV, CRD), pp. 559–564.

DAC-2005-NieKT #incremental #layout

A watermarking system for IP protection by a post layout incremental router (TN, TK, MT), pp. 218–221.

DATE-2005-BjerregaardS #architecture

A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip (TB, JS), pp. 1226–1231.

DATE-DF-2004-ZeferinoKS #named

RASoC: A Router Soft-Core for Networks-on-Chip (CAZ, MEK, AAS), pp. 198–205.

SAC-2004-GalandM #architecture #functional #self

A functional architecture for self-aware routers (DG, OM), pp. 352–356.

DATE-2003-RijpkemaGRDMWW #design #network

Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip (ER, KGWG, AR, JD, JLvM, PW, EW), pp. 10350–10355.

DAC-2002-YeMB #analysis #network #power management

Analysis of power consumption on switch fabrics in network routers (TTY, GDM, LB), pp. 524–529.

ASPLOS-2002-KohlerMC #composition #optimisation #programming language

Programming language optimizations for modular router configurations (EK, RM, BC), pp. 251–263.

ASPLOS-2002-MukherjeeSBELW #algorithm #case study #comparative #pipes and filters

A comparative study of arbitration algorithms for the Alpha 21364 pipelined router (SSM, FS, PJB, JSE, SL, DW), pp. 223–234.

DATE-2001-BensoCNP #analysis #distributed #fault #injection #open source

SEU effect analysis in an open-source router via a distributed fault injection environment (AB, SDC, GDN, PP), pp. 219–225.

DATE-2001-LienigJA #approach #named

AnalogRouter: a new approach of current-driven routing for analog circuits (JL, GJ, TA), p. 819.

SAC-2001-HaginoHTN #mobile

Location management of mobile hosts by grouping routers (HH, TH, MT, SN), pp. 373–380.

HPCA-2001-PehD #architecture #pipes and filters

A Delay Model and Speculative Architecture for Pipelined Routers (LSP, WJD), pp. 255–266.

SOSP-2001-SpalinkKPG #network #robust #using

Building a Robust Software-Based Router Using Network Processors (TS, SK, LLP, YG), pp. 216–229.

HPCA-2000-YumVDS

Investigating QoS Support for Traffic Mixes with the MediaWorm Router (KHY, ASV, CRD, AS), pp. 97–106.

HPCA-1999-DuatoYCLQ #architecture #design #multi #named #trade-off

MMR: A High-Performance Multimedia Router — Architecture and Design Trade-Offs (JD, SY, BC, DSL, FJQ), pp. 300–309.

HPCA-1999-VaidyaSD #adaptation #design #named #performance

LAPSES: A Recipe for High Performance Adaptive Router Design (ASV, AS, CRD), pp. 236–243.

SOSP-1999-MorrisKJK #composition

The Click modular router (RM, EK, JJ, MFK), pp. 217–231.

DATE-1998-AdlerS #design #interactive

An Interactive Router for Analog IC Design (TA, JS), pp. 414–420.

DATE-1998-Hetzel #graph #grid

A Sequential Detailed Router for Huge Grid Graphs (AH), pp. 332–338.

DATE-1998-WangK #reduction

A Performance-Driven MCM Router with Special Consideration of Crosstalk Reduction (DW, ESK), pp. 466–470.

EDTC-1997-TsengS #multi #standard #using

A gridless multi-layer router for standard cell circuits using CTM cells (HPT, CS), pp. 319–326.

HPCA-1996-ChalasaniB #fault tolerance #multi

Fault-Tolerance with Multimodule Routers (SC, RVB), pp. 201–210.

DAC-1995-LeeW #performance

A Performance and Routability Driven Router for FPGAs Considering Path Delays (YSL, ACHW), pp. 557–561.

DAC-1994-HaradaK #optimisation #performance

A Global Router Optimizing Timing and Area for High-Speed Bipolar LSI’s (IH, HK), pp. 177–181.

EDAC-1994-WuM #2d #array #performance #programmable

An Efficient Router for 2-D Field Programmable Gate Arrays (YLW, MMS), pp. 412–416.

DAC-1993-KhooC #multi #performance

An Efficient Multilayer MCM Router Based on Four-Via Routing (KYK, JC), pp. 590–595.

DAC-1992-FujiiMMY #multi

A Multi-Layer Channel Router with New Style of Over-the-Cell Routing (TF, YM, TM, TY), pp. 585–588.

DAC-1992-Palczewski #parallel

Plane Parallel a Maze Router and Its Application to FPGAs (MP), pp. 691–697.

DAC-1992-WuSHS

Over-the-Cell Routers for New Cell Model (BW, NAS, NDH, MS), pp. 604–607.

DAC-1991-CardenC #algorithm #approximate #multi #performance #using

A Global Router Using An Efficient Approximate Multicommodity Multiterminal Flow Algorithm (RCCI, CKC), pp. 316–321.

DAC-1991-GuruswamyW #multi

A General Multi-Layer Area Router (MG, DFW), pp. 335–340.

DAC-1990-BrouwerB #named #parallel

PHIGURE: A Parallel Hierarchical Global Router (RJB, PB), pp. 650–653.

DAC-1990-GidwaniS #named

MISER: An Integrated Three Layer Gridless Channel Router and Compactor (RAG, NAS), pp. 698–703.

DAC-1990-KatsadasK #multi

A Multi-Layer Router Utilizing Over-Cell Areas (EK, EK), pp. 704–708.

DAC-1990-SchieleKJK #design #industrial

A Gridless Router for Industrial Design Rules (WLS, TK, KMJ, FHK), pp. 626–631.

DAC-1988-ArnoldS #interactive

An Interactive Maze Router with Hints (MHA, WSS), pp. 672–676.

DAC-1988-HeynsN #recursion

Recursive Channel Router (WH, KVN), pp. 178–182.

DAC-1988-Lunow #multi

A Channelless, Multilayer Router (REL), pp. 667–671.

DAC-1988-Rose #named #parallel #standard

LocusRoute: A Parallel Global Router for Standard Cells (JR), pp. 189–195.

PPEALS-1988-Rose #composition #implementation #parallel

The Parallel Decomposition and Implementation of an Integrated Circuit Global Router (JR), pp. 138–145.

DAC-1987-EnbodyD

General Purpose Router (RJE, HCD), pp. 637–640.

DAC-1987-HsuPK

A Path Selection Global Router (YCH, YP, WJK), pp. 641–644.

DAC-1987-McGehee

A Practical Moat Router (RKM), pp. 216–222.

DAC-1987-Ng #design

A “gridless” Variable-Width Channel Router for Marco Cell Design (CHN), pp. 633–636.

DAC-1987-Polkl

A Three-Layer Gridless Channel Router with Compaction (DBP), pp. 146–151.

DAC-1987-Rosenberg87a #interactive

A New Interactive Supply/Demand Router with Rip-Up Capability for Printed Circuit Boards (ER), pp. 721–726.

DAC-1986-BobbaS

A parameter-driven router (VSB, JWS), pp. 810–818.

DAC-1986-BraunBDMMRS #multi #named

Chameleon: a new multi-layer channel router (DB, JLB, SD, HKTM, KM, FR, ALSV), pp. 495–502.

DAC-1986-KawamuraUS

Hierarchical dynamic router (KK, MU, HS), pp. 803–809.

DAC-1986-KessenichJ

Global forced hierarchical router (JK, GJ), pp. 798–802.

DAC-1986-Ng #industrial

An industrial world channel router for non-rectangular channels (CHN), pp. 490–494.

DAC-1986-TadaH #performance #scalability

Router system for printed wiring boards of very high-speed, very large-scale computers (TT, AH), pp. 791–797.

DAC-1985-DwyerMBG #array #automation #design #integration

The integration of an advanced gate array router into a fully automated design system (RD, SM, EB, DG), pp. 770–772.

DAC-1985-Marek-Sadowska #2d #layout

Two-dimensional router for double layer layout (MMS), pp. 117–123.

DAC-1984-HamachiO

A switchbox router with obstacle avoidance (GTH, JKO), pp. 173–179.

DAC-1984-Mori #interactive #layout

Interactive compaction router for VLSI layout (HM), pp. 137–143.

DAC-1984-Ng #design

A symbolic-interconnect router for custom IC design (CHN), pp. 52–58.

DAC-1984-Yoshimura #performance

An efficient channel router (TY), pp. 38–44.

DAC-1983-BursteinP

Hierarchical channel router (MB, RNP), pp. 591–597.

DAC-1983-Krohn #array

An over-cell gate array channel router (HEK), pp. 665–670.

DAC-1982-Asano #parametricity

Parametric pattern router (TA), pp. 411–417.

DAC-1982-Heyns #algorithm

The 1-2-3 routing algorithm or the single channel 2-step router on 3 interconnection layers (WH), pp. 113–120.

DAC-1982-Korn #performance

An efficient variable-cost maze router (RKK), pp. 425–431.

DAC-1982-LieH #layout

A bus router for IC layout (ML, CSH), pp. 129–132.

DAC-1982-RaghavanS

Optimal single row router (RR, SS), pp. 38–45.

DAC-1982-RivestF

A “greedy” channel router (RLR, CMF), pp. 418–424.

DAC-1981-TsuiS #multi

A high-density multilayer PCB router based on necessary and sufficient conditions for single row routing (RYT, RJSI), pp. 372–381.

DAC-1981-Wada

A dogleg “optimal” channel router with completion enhancements (MMW), pp. 762–768.

DAC-1980-DeutschG

An over-the-cell router (DND, PG), pp. 32–39.

DAC-1980-HightowerB

A generalized channel router (DWH, RLB), pp. 12–21.

DAC-1980-LorenzettiS #implementation #multi

An implementation of a saturated zone multi-layer printed circuit board router (MJL, RJSI), pp. 255–262.

DAC-1980-SatoSNOY

A “grid-free” channel router (KS, HS, TN, MO, TY), pp. 22–31.

DAC-1980-TadaYKS #performance #strict

A fast maze router with iterative use of variable search space restriction (FT, KY, TK, TS), pp. 250–254.

DAC-1979-Foster #lookahead #multi

A “lookahead” router for multilayer printed wiring boards (JCF), pp. 486–493.

DAC-1979-Soukup

Global router (JS), pp. 481–484.

DAC-1978-Soukup #performance

Fast maze router (JS), pp. 100–102.

DAC-1977-CageS #multi

A rectangle-probe router for multilayer P.C. boards (WGC, RJSI), pp. 13–22.

DAC-1976-Allen #adaptation

A topologically adaptable cellular router (JRA), pp. 161–167.

DAC-1976-Deutsch

A “Dogleg” channel router (DND), pp. 425–433.

DAC-1976-WilsonS #comparison

An analytic technique for router comparison (DCW, RJSI), pp. 251–258.

DAC-1974-SlemakerMLL #programmable

A programmable printed-wiring router (CSS, RCM, LWL, AGL), pp. 314–321.

DAC-1973-Foster #multi

A router for multilayer printed wiring backplanes (JCF), pp. 44–49.

DAC-1972-Mattison #low cost #quality

A high quality, low cost router for MOS/LSI (RLM), pp. 94–103.