Travelled to:3 × USA
Collaborated with:D.H.Du J.A.Ludwig K.Eng S.H.Yen
Talks about:placement (1) dimension (1) construct (1) synthesi (1) synchron (1) perform (1) circuit (1) sensit (1) matrix (1) layout (1)
Person: Ichiang Lin
DBLP: Lin:Ichiang
Contributed to:
199219901989Wrote 3 papers:
- DAC-1992-LinLE
- Analyzing Cycle Stealing on Synchronous Circuits with Level-Sensitive Latches (IL, JAL, KE), pp. 393–398.
- DAC-1990-LinD
- Performance-Driven Constructive Placement (IL, DHCD), pp. 103–106.
- DAC-1989-LinDY #2d #layout #matrix #synthesis
- Gate Matrix Layout Synthesis with Two-Dimensional Folding (IL, DHCD, SHCY), pp. 37–42.