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Travelled to:
4 × France
4 × Germany
Collaborated with:
W.Rosenstiel W.Nebel J.Oetjens R.Lissel A.G.Braun D.Lettnin J.Ruf T.Kropf R.Görgen J.B.Freuer G.Jerke M.Bogdan T.Schubert J.Hanisch J.Appell D.W.Hoffmann W.Müller M.Müller D.Nienhüser J.M.Zöllner O.Bringmann P.K.Nalla J.Behrend V.Schönknecht S.Reitemeyer
Talks about:
design (7) automot (4) system (4) flow (4) verif (3) transform (2) hardwar (2) high (2) base (2) methodolog (1)

Person: Joachim Gerlach

DBLP DBLP: Gerlach:Joachim

Contributed to:

DATE 20102010
DATE 20092009
DATE 20082008
DATE 20072007
DATE Designers’ Forum 20062006
DATE DF 20042004
DATE 20012001
DATE 19981998

Wrote 10 papers:

DATE-2010-MullerBGRNZB #design #implementation #manycore #recognition
Design of an automotive traffic sign recognition system targeting a multi-core SoC implementation (MM, AGB, JG, WR, DN, JMZ, OB), pp. 532–537.
DATE-2009-LettninNBRGKRSR #hardware #verification
Semiformal verification of temporal properties in automotive hardware dependent software (DL, PKN, JB, JR, JG, TK, WR, VS, SR), pp. 1214–1217.
DATE-2009-OetjensGGN #automation #hardware #process
An automated flow for integrating hardware IP into the automotive systems engineering process (JHO, RG, JG, WN), pp. 1196–1201.
DATE-2008-FreuerJGN #constraints #design #higher-order #on the #verification
On the Verification of High-Order Constraint Compliance in IC Design (JBF, GJ, JG, WN), pp. 26–31.
DATE-2007-LisselGG #design #industrial #perspective #verification
Introducing new verification methods into a company’s design flow: an industrial user’s point of view (RL, JG), pp. 689–694.
DATE-DF-2006-OetjensGR #design #flexibility #rule-based #specification
Flexible specification and application of rule-based transformations in an automotive design flow (JHO, JG, WR), pp. 82–87.
DATE-DF-2004-LettninBBGR #case study #design #embedded #network #synthesis
Synthesis of Embedded SystemC Design: A Case Study of Digital Neural Networks (DL, AGB, MB, JG, WR), pp. 248–255.
DATE-DF-2004-SchubertHGAN #design #evaluation
Evaluation of a Refinement-Driven SystemC™-Based Design Flow (TS, JH, JG, JEA, WN), pp. 262–267.
DATE-2001-RufHGKRM #semantics #simulation
The simulation semantics of systemC (JR, DWH, JG, TK, WR, WM), pp. 64–70.
DATE-1998-GerlachR #design #estimation #scalability
A Scalable Methodology for Cost Estimation in a Transformational High-Level Design Space Exploration Environment (JG, WR), pp. 226–231.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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