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Travelled to:
1 × France
1 × USA
4 × Germany
Collaborated with:
J.Lienig A.B.Kahng J.Scheible T.Adler M.Mittag A.Krinke W.Rosenstiel J.B.Freuer J.Gerlach W.Nebel
Talks about:
design (4) analog (3) electromigr (2) constraint (2) hierarch (2) current (2) circuit (2) driven (2) verif (2) decompact (1)

Person: Göran Jerke

DBLP DBLP: Jerke:G=ouml=ran

Contributed to:

DATE 20142014
DATE 20122012
DATE 20082008
DAC 20042004
DATE 20022002
DATE 20012001

Wrote 6 papers:

DATE-2014-JerkeK #case study #design
Mission profile aware IC design — A case study (GJ, ABK), pp. 1–6.
DATE-2012-MittagKJR #constraints #design #geometry #physics
Hierarchical propagation of geometric constraints for full-custom physical design of ICs (MM, AK, GJ, WR), pp. 1471–1474.
DATE-2008-FreuerJGN #constraints #design #higher-order #on the #verification
On the Verification of High-Order Constraint Compliance in IC Design (JBF, GJ, JG, WN), pp. 26–31.
DAC-2004-JerkeLS #design #layout
Reliability-driven layout decompaction for electromigration failure avoidance in complex mixed-signal IC designs (GJ, JL, JS), pp. 181–184.
DATE-2002-JerkeL #analysis #verification
Hierarchical Current Density Verification for Electromigration Analysis in Arbitrary Shaped Metallization Patterns of Analog Circuits (GJ, JL), pp. 464–469.
DATE-2001-LienigJA #approach #named
AnalogRouter: a new approach of current-driven routing for analog circuits (JL, GJ, TA), p. 819.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.