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XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
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Travelled to:
1 × France
4 × USA
Collaborated with:
S.Lin V.W.Hsiao C.Lin H.Zhang M.D.F.Wong Y.Chang H.Gräb F.Balasa R.Castro-López Y.Chang F.V.Fernández M.Strasser
Talks about:
analog (4) placement (3) base (2) capacitor (1) synthesi (1) symmetri (1) hierarch (1) approach (1) topolog (1) thermal (1)

Person: Mark Po-Hung Lin

DBLP DBLP: Lin:Mark_Po=Hung

Contributed to:

DAC 20142014
DAC 20092009
DATE 20092009
DAC 20082008
DAC 20072007

Wrote 5 papers:

Parasitic-aware Sizing and Detailed Routing for Binary-weighted Capacitors in Charge-scaling DAC (MPHL, VWHH, CYL), p. 6.
Thermal-driven analog placement considering device matching (MPHL, HZ, MDFW, YWC), pp. 593–598.
DATE-2009-GrabBCCFLS #layout #synthesis
Analog layout synthesis — Recent advances in topological approaches (HG, FB, RCL, YWC, FVF, MPHL, MS), pp. 274–279.
DAC-2008-LinL #clustering
Analog placement based on hierarchical module clustering (MPHL, SCL), pp. 50–55.
DAC-2007-LinL #novel #symmetry
Analog Placement Based on Novel Symmetry-Island Formulation (MPHL, SCL), pp. 465–470.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.