BibSLEIGH corpus
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Open Knowledge
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Travelled to:
3 × Germany
4 × France
Collaborated with:
J.Raik A.Morawiec S.Devadze A.Jutman M.Gorev Z.Peng A.Benso P.Prinetto M.Rebaudengo M.S.Reorda A.Schneider K.Diener E.Ivask P.Miklos T.Cibáková E.Gramatová
Talks about:
simul (5) diagram (4) decis (4) level (3) fault (3) base (3) parallel (2) generat (2) circuit (2) critic (2)

Person: Raimund Ubar

DBLP DBLP: Ubar:Raimund

Contributed to:

DATE 20152015
DATE 20102010
DATE 20022002
DATE 20012001
DATE 20002000
DATE 19991999
ED&TC 19971997

Wrote 8 papers:

DATE-2015-GorevUD #fault #parallel #simulation
Fault simulation with parallel exact critical path tracing in multiple core environment (MG, RU, SD), pp. 1180–1185.
DATE-2010-UbarDRJ #parallel #simulation
Parallel X-fault simulation with critical path tracing technique (RU, SD, JR, AJ), pp. 879–884.
DATE-2002-SchneiderDIRUMCG #collaboration #generative #testing
Internet-Based Collaborative Test Generation with MOSCITO (AS, KHD, EI, JR, RU, PM, TC, EG), pp. 221–226.
DATE-2001-UbarJP #diagrams #simulation
Timing simulation of digital circuits with binary decision diagrams (RU, AJ, ZP), pp. 460–466.
DATE-2000-MorawiecUR #algorithm #diagrams #simulation #using
Cycle-Based Simulation Algorithms for Digital Systems Using High-Level Decision Diagrams (AM, RU, JR), p. 743.
DATE-1999-RaikU #diagrams #generative #modelling #testing #using
Sequential Circuit Test Generation Using Decision Diagram Models (JR, RU), pp. 736–740.
DATE-1999-UbarRM #diagrams #simulation
Cycle-based Simulation with Decision Diagrams (RU, JR, AM), pp. 454–458.
EDTC-1997-BensoPRRU #approach #fault #graph #low level
A new approach to build a low-level malicious fault list starting from high-level description and alternative graphs (AB, PP, MR, MSR, RU), pp. 560–565.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.