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Travelled to:
1 × France
1 × Germany
9 × USA
Collaborated with:
T.Sherwood Y.Meng J.Oberg A.Irturk F.Fallah A.Kaplan P.Brisk M.Sarrafzadeh M.Tiwari W.Gong W.Hu A.Hosangadi E.Bozorgzadeh S.Meiklejohn G.Wang B.DeRenzi A.Arfaee N.Laptev A.P.Brown R.A.Iltis H.Lee X.Hao F.Brewer X.Li V.Kashyap J.K.Oberg V.R.Rajarathinam B.Hardekopf F.T.Chong
Talks about:
reduct (3) optim (3) level (3) communic (2) hardwar (2) channel (2) leakag (2) inform (2) effici (2) design (2)

Person: Ryan Kastner

DBLP DBLP: Kastner:Ryan

Contributed to:

ASPLOS 20142014
DATE 20132013
DAC 20112011
DAC 20102010
DAC 20092009
DAC 20062006
DATE 20062006
DAC 20052005
HPCA 20052005
DAC 20032003
DAC 20012001

Wrote 13 papers:

ASPLOS-2014-0001KOTRKSHC #named #policy #security
Sapper: a language for hardware-level security policy enforcement (XL, VK, JKO, MT, VRR, RK, TS, BH, FTC), pp. 97–112.
DATE-2013-ObergMSK #framework #hardware #testing
A practical testing framework for isolating hardware timing channels (JO, SM, TS, RK), pp. 1281–1284.
DAC-2011-ObergHITSK #data flow
Information flow isolation in I2C and USB (JO, WH, AI, MT, TS, RK), pp. 254–259.
DAC-2010-ObergHITSK #analysis #data flow
Theoretical analysis of gate level information flow tracking (JO, WH, AI, MT, TS, RK), pp. 244–247.
DAC-2009-ArfaeeILFK #linear #multi #named #performance
Xquasher: a tool for efficient computation of multiple linear expressions (AA, AI, NL, FF, RK), pp. 254–257.
DAC-2006-MengSK #embedded #power management #reduction
Leakage power reduction of embedded memories on FPGAs through location assignment (YM, TS, RK), pp. 612–617.
DAC-2006-WangGDK #design #optimisation #using
Design space exploration using time and resource duality with the ant colony optimization (GW, WG, BD, RK), pp. 451–454.
DATE-2006-HosangadiFK #optimisation #using
Optimizing high speed arithmetic circuits using three-term extraction (AH, FF, RK), pp. 1294–1299.
DATE-2006-KastnerGHBKBS #communication #layout #optimisation #synthesis
Layout driven data communication optimization for high level synthesis (RK, WG, XH, FB, AK, PB, MS), pp. 1185–1190.
DAC-2005-MengBISLK #algorithm #design #estimation #performance
MP core: algorithm and design techniques for efficient channel estimation in wireless applications (YM, APB, RAI, TS, HL, RK), pp. 297–302.
HPCA-2005-MengSK #on the #power management #reduction
On the Limits of Leakage Power Reduction in Caches (YM, TS, RK), pp. 154–165.
DAC-2003-KaplanBK #communication #configuration management #estimation #reduction
Data communication estimation and reduction for reconfigurable systems (AK, PB, RK), pp. 616–621.
DAC-2001-BozorgzadehKS #flexibility
Creating and Exploiting Flexibility in Steiner Trees (EB, RK, MS), pp. 195–198.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.