BibSLEIGH — Daniel

Travelled to:

1 × Sweden
16 × USA
3 × France
4 × Germany

Collaborated with:

S.Narayan S.Abdi F.Vahid J.Zhu F.Brewer C.Lursinsap B.Gorjiara M.Reshadi N.D.Dutt A.Gerstlauer J.Lis L.Ramachandran V.Chaiyakul L.Cai ∅ S.Bakshi N.D.Holmes E.A.Rundensteiner G.Chen N.V.Zanden Y.S.Lin A.Orailoglu D.Shin T.M.Austin S.Svoboda I.Viskic L.Yu Y.Hwang H.Cho H.Yu T.Hadley P.Kritzinger M.Olivarez J.Gong R.Potasman A.Nicolau J.Peng A.Nakamura D.Araki Y.Nishihara S.Rawat W.H.J.Jr. J.A.Darringer P.O.Pistilli H.D.Man C.Harris J.Solomon H.Schlebusch G.Smith D.Sciuto C.Mielenz C.K.Lennard F.Ghenassia S.Swan J.Kunkel E.Villar W.Rosenstiel V.Gerousis D.Barton J.Plantin S.E.Ericsson P.Cavalloro G.G.d.Jong

Talks about:

system (15) design (15) level (14) synthesi (10) generat (5) specif (5) base (5) architectur (4) interfac (4) behavior (4)

Person: Daniel Gajski

DBLP: Gajski:Daniel

Contributed to:

2010

2008

2007

2004

2003

2002

2001

1999

1998

1997

1995

1994

1993

1992

1990

1989

1988

1987

1986

1984

Wrote 42 papers:

DAC-2010-GajskiAS #question #synthesis #what: What input-language is the best choice for high level synthesis (HLS)? (DG, TMA, SS), pp. 857–858.
LCTES-2010-ViskicLG #automation #design #framework #generative #network #platform #process: Design exploration and automatic generation of MPSoC platform TLMs from Kahn Process Network applications (IV, LY, DG), pp. 77–84.
DAC-2008-GerstlauerPSGNAN #implementation #specification: Specify-explore-refine (SER): from specification to implementation (AG, JP, DS, DG, AN, DA, YN), pp. 586–591.
DAC-2008-GorjiaraG #architecture #automation #refinement: Automatic architecture refinement techniques for customizing processing elements (BG, DG), pp. 379–384.
DAC-2008-ReshadiGG #case study #design #internet #protocol: C-based design flow: a case study on G.729A for voice over internet protocol (VoIP) (MR, BG, DG), pp. 72–75.
DATE-2008-HwangAG #approximate #estimation #performance #transaction: Cycle-approximate Retargetable Performance Estimation at the Transaction Level (YH, SA, DG), pp. 3–8.
DATE-2007-ReshadiG #architecture #embedded #low level #programming: Interrupt and low-level programming support for expanding the application domain of statically-scheduled horizontal-microcoded architectures in embedded systems (MR, DG), pp. 1337–1342.
LCTES-2007-ChoAG #interface #manycore #modelling #synthesis #transaction: Interface synthesis for heterogeneous multi-core systems from transaction level models (HC, SA, DG), pp. 140–142.
DAC-2004-AbdiG #architecture #automation #functional #generative #specification: Automatic generation of equivalent architecture model from functional specification (SA, DG), pp. 608–613.
DAC-2004-CaiGG #agile #design #profiling: Retargetable profiling for rapid, early system-level design space exploration (LC, AG, DG), pp. 281–286.
DAC-2004-RawatJJDGPMHS: Were the good old days all that good?: EDA then and now (SR, WHJJ, JAD, DG, POP, HDM, CH, JS), p. 543.
DAC-2003-AbdiSG #automation #communication #design #refinement: Automatic communication refinement for system level design (SA, DS, DG), pp. 300–305.
DATE-2003-GerstlauerYG #design #modelling: RTOS Modeling for System Level Design (AG, HY, DG), pp. 10130–10135.
DATE-2003-SchlebuschSSGMLGSK #design #problem #question #transaction: Transaction Based Design: Another Buzzword or the Solution to a Design Problem? (HJS, GS, DS, DG, CM, CKL, FG, SS, JK), pp. 10876–10879.
DATE-2002-CaiGKO #design #top-down #using: Top-Down System Level Design Methodology Using SpecC, VCC and SystemC (LC, DG, PK, MO), p. 1137.
DATE-2001-GajskiVRGBPECJ #concurrent #specification: C/C++: progress or deadlock in system-level specification (DG, EV, WR, VG, DB, JP, SEE, PC, GGdJ), pp. 136–137.
DAC-1999-Gajski #design: IP-based Design Methodology (DG), p. 43.
DAC-1999-ZhuG #scheduling #synthesis: Soft Scheduling in High Level Synthesis (JZ, DG), pp. 219–224.
DATE-1999-ZhuG #design #named: OpenJ: An Extensible System Level Design Language (JZ, DG), pp. 480–484.
DAC-1998-GajskiVNG: System-level exploration with SpecSyn (DG, FV, SN, JG), pp. 812–817.
DAC-1997-BakshiG #clustering #hardware #pipes and filters: Hardware/Software Partitioning and Pipelining (SB, DG), pp. 713–716.
DAC-1995-NarayanG #generative #interface #process #protocol #using: Interfacing Incompatible Protocols Using Interface Process Generation (SN, DG), pp. 468–473.
DAC-1994-NarayanG #communication #generative #protocol: Protocol Generation for Communication Channels (SN, DG), pp. 547–551.
EDAC-1994-GajskiVN #refinement: A System-Design Methodology: Executable-Specification Refinement (DG, FV, SN), pp. 458–463.
EDAC-1994-HolmesG #algorithm #behaviour #generative: An Algorithm for Generation of Behavioral Shape Functions (NDH, DG), pp. 314–318.
EDAC-1994-NarayanG #interface #synthesis: Synthesis of System-Level Bus Interfaces (SN, DG), pp. 395–399.
EDAC-1994-RamachandranGC #algorithm #array #clustering: An Algorithm for Array Variable Clustering (LR, DG, VC), pp. 262–266.
DAC-1993-ChaiyakulGR: High-Level Transformations for Minimizing Syntactic Variances (VC, DG, LR), pp. 413–418.
DAC-1992-RundensteinerG #functional #optimisation #synthesis #using: Functional Synthesis Using Area and Delay Optimization (EAR, DG), pp. 291–296.
DAC-1992-VahidG #clustering #design #specification: Specification Partitioning for System Design (FV, DG), pp. 219–224.
DAC-1990-ChenG #behaviour #component #database #synthesis: An Intelligent Component Database for Behavioral Synthesis (GDC, DG), pp. 150–155.
DAC-1990-DuttHG #behaviour #representation #synthesis: An Intermediate Representation for Behavioral Synthesis (NDD, TH, DG), pp. 14–19.
DAC-1990-PotasmanLNG #synthesis: Percolation Based Synthesis (RP, JL, AN, DG), pp. 444–449.
DAC-1989-DuttG #behaviour #design #synthesis: Designer Controlled Behavioral Synthesis (NDD, DG), pp. 754–757.
DAC-1989-LisG #modelling #synthesis #using: VHDL Synthesis Using Structured Modeling (JL, DG), pp. 606–609.
DAC-1988-ZandenG #architecture #logic #named: MILO: A Microarchitecture and Logic Optimizer (NVZ, DG), pp. 403–408.
DAC-1987-BrewerG #architecture #design #knowledge base: Knowledge Based Control in Micro-Architecture Design (FB, DG), pp. 203–209.
DAC-1987-LinG #layout #named: LES: A Layout Expert System (YLSL, DG), pp. 672–678.
DAC-1987-LursinsapG: Improving a PLA Area by Pull-Up Transistor Folding (CL, DG), pp. 608–614.
DAC-1986-BrewerG #design #paradigm: An expert-system paradigm for design (FB, DG), pp. 62–68.
DAC-1986-OrailogluG #graph #representation: Flow graph representation (AO, DG), pp. 503–509.
DAC-1984-LursinsapG #compilation #constraints: Cell compilation with constraints (CL, DG), pp. 103–108.