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Open Knowledge
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Travelled to:
1 × France
1 × USA
Collaborated with:
G.G.E.Gielen M.Ranjan A.Agarwal H.Sampath R.Vemuri
Talks about:
circuit (2) symbol (2) analog (2) synthesi (1) perform (1) parasit (1) analysi (1) linear (1) layout (1) inclus (1)

Person: Wim Verhaegen

DBLP DBLP: Verhaegen:Wim

Contributed to:

DATE v1 20042004
DAC 20012001

Wrote 2 papers:

DATE-v1-2004-RanjanVASVG #modelling #performance #synthesis #using
Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models (MR, WV, AA, HS, RV, GGEG), pp. 604–609.
DAC-2001-VerhaegenG #analysis #linear #performance #scalability
Efficient DDD-based Symbolic Analysis of Large Linear Analog Circuits (WV, GGEG), pp. 139–144.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.