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Travelled to:
1 × USA
2 × France
Collaborated with:
H.Sampath R.Vemuri V.Yelamanchili M.Ranjan W.Verhaegen G.G.E.Gielen
Talks about:
parasit (3) circuit (2) capacit (2) layout (2) analog (2) model (2) accur (2) fast (2) awar (2) synthesi (1)

Person: Anuradha Agarwal

DBLP DBLP: Agarwal:Anuradha

Contributed to:

DAC 20042004
DATE v1 20042004
DATE v2 20042004

Wrote 3 papers:

DAC-2004-AgarwalSYV #modelling #performance
Fast and accurate parasitic capacitance models for layout-aware (AA, HS, VY, RV), pp. 145–150.
DATE-v1-2004-RanjanVASVG #modelling #performance #synthesis #using
Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models (MR, WV, AA, HS, RV, GGEG), pp. 604–609.
DATE-v2-2004-AgarwalSYV #estimation
Accurate Estimation of Parasitic Capacitances in Analog Circuits (AA, HS, VY, RV), pp. 1364–1365.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.