Travelled to:1 × Germany
1 × India
2 × France
2 × USA
Collaborated with:J.Carretero J.Abella J.Xue P.Chaparro M.Monchiero T.Ramírez A.González E.Herrero D.Gizopoulos M.Psarakis S.V.Adve P.Ramachandran S.K.S.Hari D.J.Sorin A.Meixner A.Biswas
Talks about:regist (2) file (2) architectur (1) processor (1) behaviour (1) recoveri (1) multicor (1) diagnosi (1) softwar (1) program (1)
Person: Xavier Vera
DBLP: Vera:Xavier
Contributed to:
20132011
2011201020102002Wrote 6 papers:
- DATE-2013-CarreteroHMRV
- Capturing vulnerability variations for register files (JC, EH, MM, TR, XV), pp. 1468–1473.
- DATE-2011-GizopoulosPARHSMBV #architecture #detection #fault #manycore #online
- Architectures for online error detection and recovery in multicore processors (DG, MP, SVA, PR, SKSH, DJS, AM, AB, XV), pp. 533–538.
- HPCA-2011-CarreteroVARMG #hardware #process #using
- Hardware/software-based diagnosis of load-store queues using expandable activity logs (JC, XV, JA, TR, MM, AG), pp. 321–331.
- DATE-2010-AbellaCCV
- The split register file (JA, JC, PC, XV), pp. 945–948.
- HPCA-2010-AbellaCVCG
- High-Performance low-vcc in-order core (JA, PC, XV, JC, AG), pp. 1–11.
- HPCA-2002-VeraX #behaviour
- Let’s Study Whole-Program Cache Behaviour Analytically (XV, JX), pp. 175–186.