Travelled to:1 × France
1 × United Kingdom
2 × USA
Collaborated with:S.V.Adve S.K.S.Hari M.Li H.Naeimi U.R.Karpuzcu S.K.Sahoo V.S.Adve Y.Zhou D.Gizopoulos M.Psarakis D.J.Sorin A.Meixner A.Biswas X.Vera
Talks about:fault (4) resili (2) applic (2) level (2) error (2) microarchitectur (1) architectur (1) understand (1) transient (1) processor (1)
Person: Pradeep Ramachandran
DBLP: Ramachandran:Pradeep
Contributed to:
2012
2011
20092008Wrote 4 papers:
- ASPLOS-2012-HariANR #equivalence #fault #named
- Relyzer: exploiting application-level fault equivalence to analyze application resiliency to transient faults (SKSH, SVA, HN, PR), pp. 123–134.
- DATE-2011-GizopoulosPARHSMBV #architecture #detection #fault #manycore #online
- Architectures for online error detection and recovery in multicore processors (DG, MP, SVA, PR, SKSH, DJS, AM, AB, XV), pp. 533–538.
- HPCA-2009-LiRKHA #architecture #fault #hardware #modelling
- Accurate microarchitecture-level fault modeling for studying hardware faults (MLL, PR, URK, SKSH, SVA), pp. 105–116.
- ASPLOS-2008-LiRSAAZ #comprehension #design #fault
- Understanding the propagation of hard errors to software and implications for resilient system design (MLL, PR, SKS, SVA, VSA, YZ), pp. 265–276.