Travelled to:1 × China
1 × France
1 × India
2 × Germany
7 × USA
Collaborated with:M.Zhang O.Matthews A.Meixner M.D.Hill B.F.Romanescu A.R.Lebeck R.Nathan M.M.K.Martin D.A.Wood M.Plakal A.N.Jacobvitz A.R.Calderbank J.R.Carter S.Ozev J.D.Bingham J.Erickson A.Bracy A.Condon D.Gizopoulos M.Psarakis S.V.Adve P.Ramachandran S.K.S.Hari A.Biswas X.Vera A.Ailamaki A.R.Alameldeen R.M.Dickson C.J.Mauer K.E.Moore
Talks about:coher (5) verifi (3) memori (3) detect (3) error (3) dynam (3) processor (2) translat (2) protocol (2) scalabl (2)
Person: Daniel J. Sorin
DBLP: Sorin:Daniel_J=
Contributed to:
2014
2014
201420132011
2010201020072005200220001999Wrote 13 papers:
- DAC-2014-SorinMZ #architecture #power management
- Architecting Dynamic Power Management to be Formally Verifiable (DJS, OM, MZ), p. 3.
- DATE-2014-NathanS #detection #fault #low cost #named
- Nostradamus: Low-cost hardware-only error detection for processor cores (RN, DJS), pp. 1–6.
- HPCA-2014-MatthewsZS #power management
- Scalably verifiable dynamic power management (OM, MZ, DJS), pp. 579–590.
- HPCA-2014-ZhangBES #design #named #protocol #scalability #verification
- PVCoherence: Designing flat coherence protocols for scalable verification (MZ, JDB, JE, DJS), pp. 392–403.
- HPCA-2013-JacobvitzCS #memory management
- Coset coding to extend the lifetime of memory (ANJ, ARC, DJS), pp. 222–233.
- DATE-2011-GizopoulosPARHSMBV #architecture #detection #fault #manycore #online
- Architectures for online error detection and recovery in multicore processors (DG, MP, SVA, PR, SKSH, DJS, AM, AB, XV), pp. 533–538.
- ASPLOS-2010-RomanescuLS #consistency #memory management #specification #verification
- Specifying and dynamically verifying address translation-aware memory consistency (BFR, ARL, DJS), pp. 323–334.
- HPCA-2010-RomanescuLSB #protocol
- UNified Instruction/Translation/Data (UNITD) coherence: One protocol to rule them all (BFR, ARL, DJS, AB), pp. 1–12.
- HPCA-2007-MeixnerS #detection #fault #online
- Error Detection via Online Checking of Cache Coherence with Token Coherence Signatures (AM, DJS), pp. 145–156.
- DATE-2005-CarterOS #concurrent #fault #modelling #testing
- Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown (JRC, SO, DJS), pp. 300–305.
- HPCA-2002-MartinSHW #adaptation
- Bandwidth Adaptive Snooping (MMKM, DJS, MDH, DAW), pp. 251–262.
- ASPLOS-2000-MartinSAADMMPHW #approach
- Timestamp snooping: an approach for extending SMPs (MMKM, DJS, AA, ARA, RMD, CJM, KEM, MP, MDH, DAW), pp. 25–36.
- HPCA-1999-CondonHPS #memory management #modelling #using
- Using Lamport Clocks to Reason about Relaxed Memory Models (AC, MDH, MP, DJS), pp. 270–278.