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Travelled to:
1 × France
1 × Germany
7 × USA
Collaborated with:
Y.Lin C.Hwang F.Tsai C.Hwang Y.Hsieh E.Hwang F.Vahid T.Chao J.Ho W.Jong Y.Chang B.Tabbara Y.Chen M.T.Lee B.Chen M.Fujita H.Lin C.Chou T.Hwang C.Huang Y.Chen G.Miller B.Bhattarai J.Dutt X.Chen G.Bakewell
Talks about:
cell (4) silicon (3) function (2) schedul (2) generat (2) layout (2) design (2) debug (2) path (2) data (2)

Person: Yu-Chin Hsu

DBLP DBLP: Hsu:Yu=Chin

Contributed to:

DAC 20112011
DAC 20062006
DAC 20032003
DATE 19991999
DAC 19961996
DAC 19921992
DAC 19911991
DAC 19901990

Wrote 12 papers:

DAC-2011-MillerBHDCB #analysis #testing #validation
A method to leverage pre-silicon collateral and analysis for post-silicon testing and validation (GM, BB, YCH, JD, XC, GB), pp. 575–578.
DAC-2006-HsuTJC #debugging
Visibility enhancement for silicon debug (YCH, FST, WJ, YTC), pp. 13–18.
DAC-2003-HsuTCT #debugging
Advanced techniques for RTL debugging (YCH, BT, YAC, FST), pp. 362–367.
DATE-1999-HwangVH #clustering #functional #power management
FSMD Functional Partitioning for Low Power (EH, FV, YCH), pp. 22–27.
DAC-1996-LeeHCF #design #modelling #synthesis #using
Domain-Specific High-Level Modeling and Synthesis for ATM Switch Design Using VHDL (MTCL, YCH, BC, MF), pp. 585–590.
EDAC-1994-LinCHH #design
Cell Height Driven Transistor Sizing in a Cell Based Module Design (HRL, CLC, YCH, TH), pp. 425–429.
Zero Skew Clock Net Routing (THC, YCH, JMH), pp. 518–523.
DAC-1991-HwangHL #functional #pipes and filters #scheduling
Scheduling for Functional Pipelining and Loop Winding (CTH, YCH, YLL), pp. 764–769.
DAC-1991-HwangHLH #automation #generative #layout #performance
An Efficient Layout Style for 2-Metal CMOS Leaf Cells And Their Automatic Generation (CYH, YCH, YLL, YCH), pp. 481–486.
DAC-1990-HsiehHLH #generative #layout #named
LiB: A Cell Layout Generator (YCH, CYH, YLL, YCH), pp. 474–479.
Data Path Allocation Based on Bipartite Weighted Matching (CYH, YSC, YLL, YCH), pp. 499–504.
DAC-1990-HwangHL #constraints #heuristic #scheduling
Optimum and Heuristic Data Path Scheduling Under Resource Constraints (CTH, YCH, YLL), pp. 65–70.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.