BibSLEIGH corpus
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Used together with:
test (10)
cost (5)
base (4)
circuit (4)
low (3)

Stem dft$ (all stems)

19 papers:

DATEDATE-2013-HuangMSBP #effectiveness #performance
A fast and Effective DFT for test and diagnosis of power switches in SoCs (XH, JM, RAS, SB, DKP), pp. 1089–1092.
DATEDATE-2011-BalasubramanianSMNDKMPPVT #low cost #power management #robust
Circuit and DFT techniques for robust and low cost qualification of a mixed-signal SoC with integrated power management system (LB, PS, RKM, PN, RKD, ADK, SM, SP, HP, RCV, ST), pp. 551–554.
DATEDATE-2011-KumarRPB #3d #clustering #testing
Hyper-graph based partitioning to reduce DFT cost for pre-bond 3D-IC testing (AK, SMR, IP, BB), pp. 1424–1429.
A DFT Method for Time Expansion Model at Register Transfer Level (HI, TY, HF), pp. 682–687.
DFT for controlled-impedance I/O buffers (AAAY), pp. 405–410.
DACDAC-2005-TopalogluO #approach #process
A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACs (ROT, AO), pp. 851–856.
DATEDATE-2003-NummerS #pipes and filters #testing
DFT for Testing igh-Performance Pipelined Circuits with Slow-Speed Testers (MN, MS), pp. 10212–10217.
DACDAC-2002-AbramoviciYR #low cost
Low-cost sequential ATPG with clock-control DFT (MA, XY, EMR), pp. 243–248.
DACDAC-2001-Dervisoglu #architecture #data access
A Unified DFT Architecture for Use with IEEE 1149.1 and VSIA/IEEE P1500 Compliant Test Access Controllers (BID), pp. 53–58.
DACDAC-2001-LaiC #testing
Instruction-Level DFT for Testing Processor and IP Cores in System-on-a-Chip (WCL, KTC), pp. 59–64.
DATEDATE-2001-WahlAMR #modelling #optimisation
From DFT to systems test — a model based cost optimization tool (MGW, APA, CM, MR), pp. 302–306.
CIKMCIKM-2000-WuAA00a #comparison #database #similarity
A Comparison of DFT and DWT based Similarity Search in Time-Series Databases (YLW, DA, AEA), pp. 488–495.
DATEDATE-1998-RenovellAB #implementation #multi
Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits (MR, FA, YB), pp. 815–821.
CIKMCIKM-1998-SaracEA #estimation
Iterated DFT Based Techniques for Join Size Estimation (KS, ÖE, AEA), pp. 348–355.
DACDAC-1997-ChangLMAC #approach #synthesis
A Test Synthesis Approach to Reducing BALLAST DFT Overhead (DC, MTCL, MMS, TA, KTC), pp. 466–471.
DACDAC-1994-FangG #low cost #testing
Clock Grouping: A Low Cost DFT Methodology for Delay Testing (WCF, SKG), pp. 94–99.
DACDAC-1994-ParulkarBN #representation
Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST (IP, MAB, CN), pp. 345–356.
DATEEDAC-1994-McGowenF #case study #detection
A Study of Undetectable Non-Feedback Shorts for the Purpose of Physical-DFT (RM, FJF), pp. 371–375.
DACDAC-1983-Bhavsar #algorithm #calculus #design
Design For Test Calculus: An algorithm for DFT rules checking (DKB), pp. 300–307.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.