Full chip false timing path identification: applications to the PowerPCTM microprocessors
BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
EDIT!
CC-BY
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter

Jing Zeng, Magdy S. Abadir, Jayanta Bhadra, Jacob A. Abraham
Full chip false timing path identification: applications to the PowerPCTM microprocessors
DATE, 2001.

DATE 2001
DBLP
Scholar
DOI
Full names Links ISxN
@inproceedings{DATE-2001-ZengABA,
	author        = "Jing Zeng and Magdy S. Abadir and Jayanta Bhadra and Jacob A. Abraham",
	booktitle     = "{Proceedings of the Sixth Conference on Design, Automation and Test in Europe}",
	doi           = "10.1145/367072.367361",
	isbn          = "0-7695-0993-2",
	pages         = "514--519",
	publisher     = "{ACM}",
	title         = "{Full chip false timing path identification: applications to the PowerPCTM microprocessors}",
	year          = 2001,
}

Tags:



Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.