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Travelled to:
1 × France
1 × Germany
1 × USA
Collaborated with:
M.S.Abadir J.A.Abraham L.Wang J.Bhadra
Talks about:
microprocessor (2) identif (2) power (2) time (2) path (2) fals (2) techniqu (1) approach (1) various (1) measur (1)

Person: Jing Zeng

DBLP DBLP: Zeng:Jing

Contributed to:

DAC 20022002
DATE 20012001
DATE 19981998

Wrote 3 papers:

DAC-2002-ZengAA #identification #using
False timing path identification using ATPG techniques and delay-based information (JZ, MSA, JAA), pp. 562–565.
DATE-2001-ZengABA #identification
Full chip false timing path identification: applications to the PowerPCTM microprocessors (JZ, MSA, JB, JAA), pp. 514–519.
DATE-1998-WangAZ #array #design #effectiveness #validation
Measuring the Effectiveness of Various Design Validation Approaches For PowerPC(TM) Microprocessor Arrays (LCW, MSA, JZ), pp. 273–277.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.