BibSLEIGH — Jacob_A

Travelled to:

1 × Denmark
1 × Israel
10 × USA
2 × France
6 × Germany

Collaborated with:

C.V.Gura M.S.Abadir J.Zeng H.Lee H.Kim ∅ V.M.Vedula R.Raimi H.Chang G.Ganapathy K.Roy H.Shih P.Bose J.Shen J.Park A.Chaudhari V.Viswanath W.A.H.Jr. J.Baumgartner A.Kuehlmann R.S.Tupuri A.Krishnamachary N.Nagi A.Chatterjee P.Vishakantaiah J.Chung J.Xiong V.Zolotov J.Bhadra J.Yuan A.Aziz R.P.Kunda B.D.Rathi P.Narain P.A.Duba R.K.Roy W.A.Rogers H.Cho S.Mirkhani C.Cher S.Mitra R.Vemu A.Jas S.Patil R.Galivanche D.Blaauw D.G.Saab R.B.Mueller-Thuns J.T.Rahmeh R.Mukherjee J.Jain K.Takayama M.Fujita D.S.Fussell D.Baker T.Hurson M.Kinkade G.Gervasio C.Chu G.Hu U.Schlichtmann V.Kleeberger A.Evans C.Gimmler-Dumont M.Glaß A.Herkersdorf S.R.Nassif N.Wehn

Talks about:

test (8) generat (6) microprocessor (5) time (5) path (5) use (5) techniqu (4) automat (4) verif (4) power (4)

Person: Jacob A. Abraham

DBLP: Abraham:Jacob_A=

Contributed to:

2014

2013

2012

2011

2008

2006

2002

2001

1999

1997

1993

1992

1990

1989

1988

1986

1982

Wrote 30 papers:

DATE-2014-LeeA #architecture #hybrid #novel #power management #using: A novel low power 11-bit hybrid ADC using flash and delay line architectures (HCL, JAA), pp. 1–4.
DATE-2014-SchlichtmannKAEGGHNW #abstraction #design: Connecting different worlds — Technology abstraction for reliability-aware design and Test (US, VK, JAA, AE, CGD, MG, AH, SRN, NW), pp. 1–8.
DAC-2013-ChoMCAM #design #evaluation #fault #injection #robust: Quantitative evaluation of soft error injection techniques for robust system design (HC, SM, CYC, JAA, SM), p. 10.
DATE-2013-ParkCA #energy: Non-speculative double-sampling technique to increase energy-efficiency in a high-performance processor (JP, AC, JAA), pp. 254–257.
DATE-2012-KimA #interface: On-chip source synchronous interface timing test scheme with calibration (HK, JAA), pp. 1146–1149.
DAC-2011-ChungXZA #statistics #testing: Testability driven statistical path selection (JC, JX, VZ, JAA), pp. 417–422.
DATE-2008-Abraham #dependence #roadmap: Implications of Technology Trends on System Dependability (JAA), p. 940.
DATE-2008-VemuJAPG #concurrent #detection #fault #logic #low cost: A low-cost concurrent error detection technique for processor control logic (RV, AJ, JAA, SP, RG), pp. 897–902.
DATE-2006-ViswanathAJ #automation #pipes and filters #power management: Automatic insertion of low power annotations in RTL for pipelined microprocessors (VV, JAA, WAHJ), pp. 496–501.
CAV-2002-BaumgartnerKA #analysis: Property Checking via Structural Analysis (JB, AK, JAA), pp. 151–165.
DAC-2002-ZengAA #identification #using: False timing path identification using ATPG techniques and delay-based information (JZ, MSA, JAA), pp. 562–565.
DATE-2002-VedulaA #analysis #functional #generative #named #testing: FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis (VMV, JAA), pp. 730–734.
DATE-2001-ZengABA #identification: Full chip false timing path identification: applications to the PowerPCTM microprocessors (JZ, MSA, JB, JAA), pp. 514–519.
DAC-1999-RaimiA #detection: Detecting False Timing Paths: Experiments on PowerPC Microprocessors (RR, JAA), pp. 737–741.
DAC-1999-ShenABHKGCH #functional #verification: Functional Verification of the Equator MAP1000 Microprocessor (JS, JAA, DB, TH, MK, GG, CcC, GH), pp. 169–174.
DAC-1999-TupuriKA #automation #constraints #functional #generative #testing #using: Test Generation for Gigahertz Processors Using an Automatic Functional Constraint Extractor (RST, AK, JAA), pp. 647–652.
DATE-1999-MukherjeeJTFAF #approach #performance #verification: An Efficient Filter-Based Approach for Combinational Verification (RM, JJ, KT, MF, JAA, DSF), pp. 132–137.
CAV-1997-YuanSAA #on the #verification: On Combining Formal and Informal Verification (JY, JS, JAA, AA), pp. 376–387.
DAC-1993-ChangA #named #performance: VIPER: An Efficient Vigorously Sensitizable Path Extractor (HC, JAA), pp. 112–117.
DAC-1993-GanapathyA #pseudo: Selective Pseudo Scan: Combinational ATPG with Reduced Scan in a Full Custom RISC Microprocessor (GG, JAA), pp. 550–555.
DAC-1993-NagiCA #fault #named: DRAFTS: Discretized Analog Circuit Fault Simulator (NN, AC, JAA), pp. 509–514.
DAC-1992-VishakantaiahAA #automation: Automatic Test Knowledge Extraction from VHDL (ATKET) (PV, JAA, MSA), pp. 273–278.
DAC-1990-KundaARN #generative #testing #using: Speed Up of Test Generation Using High-Level Primitives (RPK, JAA, BDR, PN), pp. 594–599.
DAC-1989-BlaauwSMAR #automation #behaviour #generative #modelling: Automatic Generation of Behavioral Models from Switch-Level Descriptions (DB, DGS, RBMT, JAA, JTR), pp. 179–184.
DAC-1989-GuraA: Average Interconnection Length and Interconnection Distribution Based on Rent’s Rule (CVG, JAA), pp. 574–577.
DAC-1989-RoyA #approach #novel #using #verification: A Novel Approach to Accurate Timing Verification Using RTL Descriptions (KR, JAA), pp. 638–641.
DAC-1988-DubaRAR #distributed #fault #simulation: Fault Simulation in a Distributed Environment (PAD, RKR, JAA, WAR), pp. 686–691.
DAC-1988-GuraA #simulation: Improved Methods of Simulating RLC Couple and Uncoupled Transmission Lines Based on the Method of Characteristics (CVG, JAA), pp. 300–305.
DAC-1986-ShihA #generative #physics #testing: Transistor-level test generation for physical failures in CMOS circuits (HCS, JAA), pp. 243–249.
DAC-1982-BoseA #array #generative #logic #programmable #testing: Test generation for programmable logic arrays (PB, JAA), pp. 574–580.