BibSLEIGH corpus
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Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
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Travelled to:
1 × France
1 × Germany
Collaborated with:
C.Chang C.H.Wen J.Zeng M.S.Abadir J.A.Abraham
Talks about:
microprocessor (1) diagnosi (1) process (1) identif (1) variat (1) design (1) applic (1) scale (1) power (1) first (1)

Person: Jayanta Bhadra

DBLP DBLP: Bhadra:Jayanta

Contributed to:

DATE 20132013
DATE 20012001

Wrote 2 papers:

DATE-2013-ChangWB #design
Process-variation-aware Iddq diagnosis for nano-scale CMOS designs — the first step (CLC, CHPW, JB), pp. 454–457.
DATE-2001-ZengABA #identification
Full chip false timing path identification: applications to the PowerPCTM microprocessors (JZ, MSA, JB, JAA), pp. 514–519.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.