BibSLEIGH — Magdy_S

Travelled to:

13 × USA
2 × Germany
5 × France

Collaborated with:

L.Wang J.Zeng J.A.Abraham P.Bastani N.Callegari H.K.Reghbati D.G.Drmanac A.G.Veneris K.Cheng A.Sen V.Ogale B.N.Lee A.J.v.d.Goor A.Carlin N.Krishnamurthy P.Vishakantaiah W.Chen J.Bhadra T.M.Mak J.B.Liu M.Amiri J.Bhadra M.Pandey R.Raimi R.E.Bryant N.Sumikawa L.Winemberg H.Mangassarian S.Safarpour F.N.Najm D.Wassung Y.Zorian M.Bapst C.Harris A.Krstic J.Liou A.Khajeh A.Gupta N.Dutt F.J.Kurdahi A.M.Eltawil K.S.Khouri

Talks about:

time (6) test (6) design (5) use (5) diagnosi (4) verif (4) microprocessor (3) statist (3) memori (3) power (3)

Person: Magdy S. Abadir

DBLP: Abadir:Magdy_S=

Contributed to:

2014

2013

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

2001

1998

1997

1992

1984

Wrote 22 papers:

DAC-2014-WangA #constraints #data mining #mining: Data Mining In EDA — Basic Principles, Promises, and Constraints (LCW, MSA), p. 6.
DAC-2013-ChenWBA #random #reuse #simulation #verification: Simulation knowledge extraction and reuse in constrained random processor verification (WC, LCW, JB, MSA), p. 6.
DATE-2011-DrmanacSWWA #multi #optimisation #parametricity #predict #testing: Multidimensional parametric test set optimization of wafer probe data for predicting in field failures and setting tighter test limits (DGD, NS, LW, LCW, MSA), pp. 794–799.
DAC-2010-CallegariDWA #classification #learning #using: Classification rule learning using subgroup discovery of cross-domain attributes responsible for design-silicon mismatch (NC, DGD, LCW, MSA), pp. 374–379.
DATE-2009-KhajehGDKEKA #design #memory management #named #reliability: TRAM: A tool for Temperature and Reliability Aware Memory Design (AK, AG, ND, FJK, AME, KSK, MSA), pp. 340–345.
DAC-2008-BastaniCWA #statistics: Statistical diagnosis of unmodeled systematic timing effects (PB, NC, LCW, MSA), pp. 355–360.
DAC-2008-SenOA #multi #predict #runtime #verification: Predictive runtime verification of multi-processor SoCs in SystemC (AS, VO, MSA), pp. 948–953.
DAC-2007-WangBA #correlation #data mining #mining #perspective: Design-Silicon Timing Correlation A Data Mining Perspective (LCW, PB, MSA), pp. 384–389.
DATE-2007-MangassarianVSNA #estimation #process #pseudo #satisfiability #using: Maximum circuit activity estimation using pseudo-boolean satisfiability (HM, AGV, SS, FNN, MSA), pp. 1538–1543.
DAC-2006-LeeWA #analysis #statistics: Refined statistical static timing analysis through (BNL, LCW, MSA), pp. 149–154.
DAC-2005-WassungZABH #design: Choosing flows and methodologies for SoC design (DW, YZ, MSA, MB, CH), p. 167.
DAC-2004-WangMCA #learning #on the: On path-based learning and its applications in delay test and diagnosis (LCW, TMM, KTC, MSA), pp. 492–497.
DATE-2003-KrsticWCLA #fault #modelling #statistics: Delay Defect Diagnosis Based Upon Statistical Timing Models — The First Step (AK, LCW, KTC, JJL, MSA), pp. 10328–10335.
DAC-2002-ZengAA #identification #using: False timing path identification using ATPG techniques and delay-based information (JZ, MSA, JAA), pp. 562–565.
DATE-2002-GoorAC #fault: Minimal Test for Coupling Faults in Word-Oriented Memories (AJvdG, MSA, AC), pp. 944–948.
DATE-2002-VenerisLAA #fault #incremental #multi: Incremental Diagnosis and Correction of Multiple Faults and Errors (AGV, JBL, MA, MSA), pp. 716–721.
DATE-2001-ZengABA #identification: Full chip false timing path identification: applications to the PowerPCTM microprocessors (JZ, MSA, JB, JAA), pp. 514–519.
DAC-1998-WangAK #array #automation #evaluation #generative #using #verification: Automatic Generation of Assertions for Formal Verification of PowerPC Microprocessor Arrays Using Symbolic Trajectory Evaluation (LCW, MSA, NK), pp. 534–537.
DATE-1998-WangAZ #array #design #effectiveness #validation: Measuring the Effectiveness of Various Design Validation Approaches For PowerPC(TM) Microprocessor Arrays (LCW, MSA, JZ), pp. 273–277.
DAC-1997-PandeyRBA #evaluation #using #verification: Formal Verification of Content Addressable Memories Using Symbolic Trajectory Evaluation (MP, RR, REB, MSA), pp. 167–172.
DAC-1992-VishakantaiahAA #automation: Automatic Test Knowledge Extraction from VHDL (ATKET) (PV, JAA, MSA), pp. 273–278.
DAC-1984-AbadirR #case study #generative #testing: Test generation for LSI: A case study (MSA, HKR), pp. 180–195.