Proceedings of the 10th International Conference on High-Performance Computer Architecture
HPCA, 2004.

@proceedings{HPCA-2004,
	address       = "Madrid, Spain",
	ee            = "http://www.computer.org/csdl/proceedings/hpca/2004/2053/00/index.html",
	isbn          = "0-7695-2053-7",
	publisher     = "{IEEE Computer Society}",
	title         = "{Proceedings of the 10th International Conference on High-Performance Computer Architecture}",
	year          = 2004,
}

Contents (27 items)

5 ×#using
4 ×#predict
3 ×#scheduling
2 ×#branch
2 ×#energy
2 ×#memory management
2 ×#multi
2 ×#power management

HPCA-2004-WenWPK #predict

Exploiting Prediction to Reduce Power on Buses (VW, MW, YP, JK), pp. 2–13.

HPCA-2004-LiMH #energy #multi

The Thrifty Barrier: Energy-Aware Synchronization in Shared-Memory Multiprocessors (JL, JFM, MCH), pp. 14–23.

HPCA-2004-GniadyHL #power management

Program Counter Based Techniques for Dynamic Power Management (CG, YCH, YHL), pp. 24–35.

HPCA-2004-JosephHM #analysis #case study #design #experience

Wavelet Analysis for Microprocessor Design: Experiences with Wavelet-Based dI/dt Characterization (RJ, ZH, MM), pp. 36–47.

HPCA-2004-CristalOLV #commit

Out-of-Order Commit Processors (AC, DO, JL, MV), pp. 48–59.

HPCA-2004-JayasenaEAD

Stream Register Files with Indexed Access (NJ, ME, JHA, WJD), pp. 60–72.

HPCA-2004-AbellaG #distributed #queue

Low-Complexity Distributed Issue Queue (JA, AG), pp. 73–83.

HPCA-2004-AamodtCHWS #hardware

Hardware Support for Prescient Instruction Prefetch (TMA, PC, PH, HW, JPS), pp. 84–95.

HPCA-2004-NesbitS #using

Data Cache Prefetching Using a Global History Buffer (KJN, JES), pp. 96–105.

HPCA-2004-KalogeropulosRRST

Processor Aware Anticipatory Prefetching in Loops (SK, MR, VR, YS, PT), pp. 106–117.

HPCA-2004-ZhuDDLZC #energy #power management #using

Reducing Energy Consumption of Disk Storage Using Power-Aware Cache Management (QZ, FMD, CFD, ZL, YZ, PC), pp. 118–129.

HPCA-2004-CarreraB #data-driven #throughput

Improving Disk Throughput in Data-Intensive Servers (EVC, RB), pp. 130–141.

HPCA-2004-ZhangSFGZN

Synthesizing Representative I/O Workloads for TPC-H (JZ, AS, HF, NG, YZ, SN), pp. 142–151.

HPCA-2004-MakineniI #architecture

Architectural Characterization of TCP/IP Packet Processing on the Pentium M Microprocessor (SM, RRI), pp. 152–163.

HPCA-2004-PengPL #performance

Signature Buffer: Bridging Performance Gap between Registers and Caches (LP, JKP, KL), pp. 164–175.

HPCA-2004-LiuSK #memory management

Organizing the Last Line of Defense before Hitting the Memory Wall for CMP (CL, AS, MTK), pp. 176–185.

HPCA-2004-Michaud #capacity #execution #manycore #migration

Exploiting the Cache Capacity of a Single-Chip Multi-Core Processor with Execution Migration (PM), pp. 186–197.

HPCA-2004-KimL #comprehension #scheduling

Understanding Scheduling Replay Schemes (IK, MHL), pp. 198–209.

HPCA-2004-NarayanasamyHSC #convergence #string #using

Creating Converged Trace Schedules Using String Matching (SN, YH, SS, BC), pp. 210–221.

HPCA-2004-EhrhartP #predict #scheduling #using

Reducing the Scheduling Critical Cycle Using Wakeup Prediction (TEE, SJP), pp. 222–231.

HPCA-2004-HuVI #scheduling

Exploring Wakeup-Free Instruction Scheduling (JSH, NV, MJI), pp. 232–243.

HPCA-2004-FalconRV #multi #thread

A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors (AF, AR, MV), pp. 244–253.

HPCA-2004-GandhiAS #branch #predict

Reducing Branch Misprediction Penalty via Selective Branch Recovery (AG, HA, STS), pp. 254–264.

HPCA-2004-AkkarySKPR #branch #estimation

Perceptron-Based Branch Confidence Estimation (HA, STS, RK, YP, WR), pp. 265–275.

HPCA-2004-ChenYFM #effectiveness #predict

Accurate and Complexity-Effective Spatial Pattern Prediction (CFC, SHY, BF, AM), pp. 276–287.

HPCA-2004-KharbutliISL #using

Using Prime Numbers for Cache Indexing to Eliminate Conflict Misses (MK, KI, YS, JL), pp. 288–299.

HPCA-2004-FernandezE #memory management

Link-Time Path-Sensitive Memory Redundancy Elimination (MF, RE), pp. 300–310.