Travelled to:1 × USA
Collaborated with:V.Rana F.Bruschi D.Sciuto I.Beretta D.Atienza
Talks about:implement (1) algorithm (1) synthesi (1) stencil (1) level (1) devic (1) loop (1) iter (1) high (1) fpga (1)
Person: Alessandro Antonio Nacci
DBLP: Nacci:Alessandro_Antonio
Contributed to:
2013Wrote 1 papers:
- DAC-2013-NacciRBSBA #algorithm #implementation #synthesis
- A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices (AAN, VR, FB, DS, IB, DA), p. 6.