BibSLEIGH corpus
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Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Travelled to:
1 × France
1 × Germany
2 × USA
Collaborated with:
D.Atienza V.Rana R.Braojos A.Y.Dogan G.Ansaloni A.A.Nacci F.Bruschi D.Sciuto F.J.Rincón N.Khaled P.R.Grassi A.Akin A.A.Nacci M.D.Santambrogio
Talks about:
implement (2) algorithm (2) perform (2) sensor (2) high (2) wireless (1) synthesi (1) synchron (1) parallel (1) chamboll (1)

Person: Ivan Beretta

DBLP DBLP: Beretta:Ivan

Contributed to:

DATE 20142014
DAC 20132013
DAC 20122012
DATE 20112011

Wrote 4 papers:

DATE-2014-BraojosDBAA #approach #hardware #manycore #power management
Hardware/software approach for code synchronization in low-power multi-core sensor nodes (RB, AYD, IB, GA, DA), pp. 1–6.
DAC-2013-NacciRBSBA #algorithm #implementation #synthesis
A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices (AAN, VR, FB, DS, IB, DA), p. 6.
DAC-2012-BerettaRKGRA #design #energy #network #trade-off
Design exploration of energy-performance trade-offs for wireless sensor networks (IB, FJR, NK, PRG, VR, DA), pp. 1043–1048.
DATE-2011-AkinBNRSA #algorithm #implementation #parallel
A high-performance parallel implementation of the Chambolle algorithm (AA, IB, AAN, VR, MDS, DA), pp. 1436–1441.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.