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Travelled to:
1 × France
2 × USA
Collaborated with:
I.Beretta D.Atienza F.Bruschi D.Sciuto F.Perini A.A.Nacci F.J.Rincón N.Khaled P.R.Grassi A.Akin A.A.Nacci M.D.Santambrogio
Talks about:
implement (2) algorithm (2) perform (2) high (2) wireless (1) synthesi (1) parallel (1) chamboll (1) cellular (1) automata (1)

Person: Vincenzo Rana

DBLP DBLP: Rana:Vincenzo

Contributed to:

DAC 20132013
DAC 20122012
DATE 20112011

Wrote 4 papers:

DAC-2013-NacciRBSBA #algorithm #implementation #synthesis
A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices (AAN, VR, FB, DS, IB, DA), p. 6.
DAC-2012-BerettaRKGRA #design #energy #network #trade-off
Design exploration of energy-performance trade-offs for wireless sensor networks (IB, FJR, NK, PRG, VR, DA), pp. 1043–1048.
DATE-2011-AkinBNRSA #algorithm #implementation #parallel
A high-performance parallel implementation of the Chambolle algorithm (AA, IB, AAN, VR, MDS, DA), pp. 1436–1441.
DATE-2011-BruschiPRS #automaton #performance
An efficient Quantum-Dot Cellular Automata adder (FB, FP, VR, DS), pp. 1220–1223.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.