Travelled to:1 × France
1 × Germany
3 × USA
Collaborated with:S.Kumar P.Pujara ∅ K.H.Randall S.Ghose L.Gilgeous P.Dudnik C.Waxman
Talks about:perform (2) detect (2) cach (2) microprocessor (1) architectur (1) techniqu (1) prefetch (1) overhead (1) instruct (1) support (1)
Person: Aneesh Aggarwal
DBLP: Aggarwal:Aneesh
Contributed to:
2009
20082006
2002
2001Wrote 6 papers:
- DATE-2009-GhoseGDAW #architecture #detection #memory management
- Architectural support for low overhead detection of memory violations (SG, LG, PD, AA, CW), pp. 652–657.
- HPCA-2008-KumarA #trade-off #validation
- Speculative instruction validation for performance-reliability trade-off (SK, AA), pp. 405–414.
- HPCA-2006-KumarA #concurrent #detection #fault #performance
- Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors (SK, AA), pp. 212–221.
- HPCA-2006-PujaraA #performance
- Increasing the cache efficiency by eliminating noise (PP, AA), pp. 145–154.
- ISMM-2002-Aggarwal
- Software caching vs. prefetching (AA), pp. 263–268.
- PLDI-2001-AggarwalR #analysis
- Related Field Analysis (AA, KHR), pp. 214–220.