BibSLEIGH corpus
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Travelled to:
3 × USA
Collaborated with:
M.A.Breuer I.Parulkar K.Lee R.Raina R.Bailey R.F.Molyneaux C.Beh
Talks about:
circuit (3) level (2) test (2) represent (1) structur (1) descript (1) switest (1) regener (1) generat (1) extract (1)

Person: Charles Njinda

DBLP DBLP: Njinda:Charles

Contributed to:

DAC 19971997
DAC 19941994
DAC 19921992

Wrote 3 papers:

DAC-1997-RainaBNMB #design #performance #testing
Efficient Testing of Clock Regenerator Circuits in Scan Designs (RR, RB, CN, RFM, CB), pp. 95–100.
DAC-1994-ParulkarBN #representation
Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST (IP, MAB, CN), pp. 345–356.
DAC-1992-LeeNB #generative #named #testing
SWiTEST: A Switch Level Test Generation System for CMOS Combinational Circuits (KJL, CN, MAB), pp. 26–29.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.