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Travelled to:
1 × France
4 × USA
Collaborated with:
M.A.Breuer S.K.Gupta C.Njinda
Talks about:
bist (4) resourc (3) schedul (2) reduc (2) data (2) represent (1) structur (1) overhead (1) introduc (1) descript (1)

Person: Ishwar Parulkar

DBLP DBLP: Parulkar:Ishwar

Contributed to:

DAC 19981998
DATE 19981998
DAC 19961996
DAC 19951995
DAC 19941994

Wrote 5 papers:

DAC-1998-ParulkarGB #behaviour
Introducing Redundant Computations in a Behavior for Reducing BIST Resources (IP, SKG, MAB), pp. 548–553.
DATE-1998-ParulkarGB #scheduling
Scheduling and Module Assignment for Reducing Bist Resources (IP, SKG, MAB), pp. 66–73.
DAC-1996-ParulkarGB #bound #data flow #graph
Lower Bounds on Test Resources for Scheduled Data Flow Graphs (IP, SKG, MAB), pp. 143–148.
DAC-1995-ParulkarGB #design
Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead (IP, SKG, MAB), pp. 395–401.
DAC-1994-ParulkarBN #representation
Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST (IP, MAB, CN), pp. 345–356.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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