Travelled to:2 × USA
Collaborated with:S.Huang C.Cheng Y.Nieh Y.Ho J.Lin H.Wang Y.Lu
Talks about:clock (3) minimum (1) period (1) insert (1) minim (1) match (1) delay (1) zero (1) type (1) tree (1)
Person: Chia-Ming Chang
DBLP: Chang:Chia=Ming
Contributed to:
20082007Wrote 2 papers:
- DAC-2008-ChangHHLWL
- Type-matching clock tree for zero skew clock gating (CMC, SHH, YKH, JZL, HPW, YSL), pp. 714–719.
- DAC-2007-HuangCCN
- Clock Period Minimization with Minimum Delay Insertion (SHH, CHC, CMC, YTN), pp. 970–975.