Travelled to:1 × France
2 × USA
Collaborated with:S.Huang Y.Nieh W.Tu C.Chang W.Yu
Talks about:clock (4) period (3) minimum (2) minim (2) path (2) synthesi (1) control (1) regist (1) insert (1) delay (1)
Person: Chun-Hua Cheng
DBLP: Cheng:Chun=Hua
Contributed to:
2013
20072006Wrote 3 papers:
- DATE-2013-TuHC
- Co-synthesis of data paths and clock control paths for minimum-period clock gating (WPT, SHH, CHC), pp. 1831–1836.
- DAC-2007-HuangCCN
- Clock Period Minimization with Minimum Delay Insertion (SHH, CHC, CMC, YTN), pp. 970–975.
- DAC-2006-HuangCNY
- Register binding for clock period minimization (SHH, CHC, YTN, WCY), pp. 439–444.