Travelled to:1 × Germany
3 × USA
Collaborated with:S.Huang C.Cheng H.Yeh F.Lu S.Hsu C.Chang W.Yu
Talks about:clock (5) minim (4) period (3) awar (2) schedul (1) opposit (1) minimum (1) current (1) regist (1) leakag (1)
Person: Yow-Tyng Nieh
DBLP: Nieh:Yow=Tyng
Contributed to:
2014
200720062005Wrote 5 papers:
- DATE-2014-YehHN #power management
- Leakage-power-aware clock period minimization (HHY, SHH, YTN), pp. 1–6.
- DAC-2007-HuangCCN
- Clock Period Minimization with Minimum Delay Insertion (SHH, CHC, CMC, YTN), pp. 970–975.
- DAC-2006-HuangCNY
- Register binding for clock period minimization (SHH, CHC, YTN, WCY), pp. 439–444.
- DAC-2005-HuangNL #scheduling
- Race-condition-aware clock skew scheduling (SHH, YTN, FPL), pp. 475–478.
- DAC-2005-NiehHH
- Minimizing peak current via opposite-phase clock tree (YTN, SHH, SYH), pp. 182–185.