Travelled to:1 × France
1 × Germany
4 × USA
Collaborated with:Y.Nieh C.Cheng C.Chang H.Yeh W.Tu F.Lu S.Hsu W.Yu Y.Ho J.Lin H.Wang Y.Lu
Talks about:clock (9) period (4) minim (4) minimum (2) tree (2) skew (2) path (2) gate (2) awar (2) synthesi (1)
Person: Shih-Hsu Huang
DBLP: Huang:Shih=Hsu
Contributed to:
20142013
2008200720062005Wrote 7 papers:
- DATE-2014-YehHN #power management
- Leakage-power-aware clock period minimization (HHY, SHH, YTN), pp. 1–6.
- DATE-2013-TuHC
- Co-synthesis of data paths and clock control paths for minimum-period clock gating (WPT, SHH, CHC), pp. 1831–1836.
- DAC-2008-ChangHHLWL
- Type-matching clock tree for zero skew clock gating (CMC, SHH, YKH, JZL, HPW, YSL), pp. 714–719.
- DAC-2007-HuangCCN
- Clock Period Minimization with Minimum Delay Insertion (SHH, CHC, CMC, YTN), pp. 970–975.
- DAC-2006-HuangCNY
- Register binding for clock period minimization (SHH, CHC, YTN, WCY), pp. 439–444.
- DAC-2005-HuangNL #scheduling
- Race-condition-aware clock skew scheduling (SHH, YTN, FPL), pp. 475–478.
- DAC-2005-NiehHH
- Minimizing peak current via opposite-phase clock tree (YTN, SHH, SYH), pp. 182–185.