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Travelled to:
1 × France
1 × Germany
2 × USA
Collaborated with:
G.D.Micheli S.Murali L.Benini F.Angiolini A.Pullini
Talks about:
chip (4) network (3) synthesi (2) topolog (2) shutdown (1) research (1) deadlock (1) wormhol (1) support (1) product (1)

Person: Ciprian Seiculescu

DBLP DBLP: Seiculescu:Ciprian

Contributed to:

DAC 20102010
DATE 20102010
DAC 20092009
DATE 20092009

Wrote 4 papers:

DAC-2010-MicheliSMBAP #network #research
Networks on Chips: from research to products (GDM, CS, SM, LB, FA, AP), pp. 300–305.
DATE-2010-SeiculescuMBM
A method to remove deadlocks in Networks-on-Chips with Wormhole flow control (CS, SM, LB, GDM), pp. 1625–1628.
DAC-2009-SeiculescuMBM #synthesis
NoC topology synthesis for supporting shutdown of voltage islands in SoCs (CS, SM, LB, GDM), pp. 822–825.
DATE-2009-SeiculescuMBM #3d #network #synthesis
SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips (CS, SM, LB, GDM), pp. 9–14.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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