BibSLEIGH — Giovanni_De

Travelled to:

11 × France
18 × USA
9 × Germany

Collaborated with:

L.Benini S.Murali P.Gaillardon ∅ L.G.Amarù T.Simunic D.Atienza M.H.B.Jamaa D.C.Ku Y.Leblebici A.Peymandoust A.Bogliolo M.Damiani E.Macii J.Smith C.Seiculescu S.Bobba M.Poncino F.Angiolini V.F.Pavlidis K.Mohanram T.T.Ye J.C.Yang S.Carrara A.Pullini M.D.Marchi D.Bertozzi S.Ercolani A.L.Sangiovanni-Vincentelli S.S.Ghoreishizadeh P.W.Glynn E.Chung D.Sacchetto C.Boero G.Odasso R.Scarsi J.Zhang H.G.Mohammadi C.Zhang H.Xu L.Séméria K.Sato P.Siegel D.L.Dill R.K.Gupta C.J.N.C.Jr. D.Filo A.Acquaviva J.M.Mendias S.Carta J.Zhang J.Olivo A.Jalabert G.A.Paleologo C.Baj-Rossi I.Taurino F.Valgimigli A.V.Sathanur M.Coenen A.Radulescu K.Goossens G.Martin R.Seepold T.Zhang Y.Lu D.Sciuto C.Silvano N.Genko R.Hermida F.Catthoor S.Stergiou L.Raffo A.Macii A.Lioy A.Ibrahim P.Hager A.Bartolini M.Arditi N.Patil A.Lin H.P.Wong S.Mitra A.Mutapcic R.Gupta S.P.Boyd P.G.D.Valle G.Paci F.Poletti X.Tang J.Sandrini M.Thammasack S.R.Omam F.Mulas M.Pittau M.Buttu F.J.Rincón M.Paselli J.Recas Q.Zhao M.Sanchez-Elez J.Penders

Talks about:

power (19) chip (16) synthesi (15) logic (14) network (12) base (12) system (11) design (11) optim (11) control (7)

Person: Giovanni De Micheli

DBLP: Micheli:Giovanni_De

Facilitated 2 volumes:

Contributed to:

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

2001

2000

1999

1998

1997

1994

1993

1992

1991

1990

1988

1983

Wrote 78 papers:

DATE-2015-GaillardonTSTOS #power management: A ultra-low-power FPGA based on monolithically integrated RRAMs (PEG, XT, JS, MT, SRO, DS, YL, GDM), pp. 1203–1208.
DATE-2015-IbrahimHBAABM #3d: Tackling the bottleneck of delay tables in 3D ultrasound imaging (AI, PH, AB, FA, MA, LB, GDM), pp. 1683–1688.
DATE-2015-MohammadiGM #fault #modelling: Fault modeling in controllable polarity silicon nanowire circuits (HGM, PEG, GDM), pp. 453–458.
DAC-2014-AmaruGM #algorithm #graph #logic #novel #optimisation #performance: Majority-Inverter Graph: A Novel Data-Structure and Algorithms for Efficient Logic Optimization (LGA, PEG, GDM), p. 6.
DATE-2014-AmaruGM #diagrams #performance: An efficient manipulation package for Biconditional Binary Decision Diagrams (LGA, PEG, GDM), pp. 1–6.
DATE-2014-GaillardonAZM #design: Advanced system on a chip design based on controllable-polarity FETs (PEG, LGA, JZ, GDM), pp. 1–6.
DAC-2013-AmaruGM #composition #logic #named #synthesis: BDS-MAJ: a BDD-based logic synthesis tool exploiting majority logic decomposition (LGA, PEG, GDM), p. 6.
DAC-2013-GaillardonMABSLM #towards #using: Towards structured ASICs using polarity-tunable Si nanowire transistors (PEG, MDM, LGA, SB, DS, YL, GDM), p. 4.
DATE-2013-AmaruGM #canonical #logic #novel #synthesis: Biconditional BDD: a novel canonical BDD for logic synthesis targeting XOR-rich circuits (LGA, PEG, GDM), pp. 1014–1017.
DATE-2013-GaillardonABMSLM: Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs (PEG, LGA, SB, MDM, DS, YL, GDM), pp. 625–630.
DATE-2013-OlivoGCM #power management: Electronic implants: power delivery and management (JO, SSG, SC, GDM), pp. 1540–1545.
DAC-2012-BobbaMLM #physics #synthesis: Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistors (SB, MDM, YL, GDM), pp. 42–47.
DAC-2012-MicheliBBTC #personalisation: Integrated biosensors for personalized medicine (GDM, CB, CBR, IT, SC), pp. 6–11.
DATE-2012-ZhangPM #3d #analysis #grid #power management: Voltage propagation method for 3-D power grid analysis (CZ, VFP, GDM), pp. 844–847.
DATE-2011-Micheli #design #logic #physics #question #synthesis: Logic synthesis and physical design: Quo vadis? (GDM), p. 50.
DATE-2011-MicheliGBVC #framework: An integrated platform for advanced diagnostics (GDM, SSG, CB, FV, SC), pp. 1454–1459.
DATE-2011-XuPM: Analytical heat transfer model for thermal through-silicon vias (HX, VFP, GDM), pp. 395–400.
DAC-2010-MicheliSMBAP #network #research: Networks on Chips: from research to products (GDM, CS, SM, LB, FA, AP), pp. 300–305.
DAC-2010-ZhangBPLWMM #correlation: Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement (JZ, SB, NP, AL, HSPW, GDM, SM), pp. 889–892.
DATE-2010-JamaaMM #logic #power management: Power consumption of logic circuits in ambipolar carbon nanotube technology (MHBJ, KM, GDM), pp. 303–306.
DATE-2010-SeiculescuMBM: A method to remove deadlocks in Networks-on-Chips with Wormhole flow control (CS, SM, LB, GDM), pp. 1625–1628.
DAC-2009-JamaaLM #array #multi: Decoding nanowire arrays fabricated with the multi-spacer patterning technique (MHBJ, YL, GDM), pp. 77–82.
DAC-2009-SeiculescuMBM #synthesis: NoC topology synthesis for supporting shutdown of voltage islands in SoCs (CS, SM, LB, GDM), pp. 822–825.
DATE-2009-BobbaZPAM #design #logic #standard #synthesis: Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis (SB, JZ, AP, DA, GDM), pp. 616–621.
DATE-2009-JamaaMM #library #logic #multi #novel #synthesis: Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis (MHBJ, KM, GDM), pp. 622–627.
DATE-2009-SathanurPBMM #clustering #design #variability: Physically clustered forward body biasing for variability compensation in nanometer CMOS design (AVS, AP, LB, GDM, EM), pp. 154–159.
DATE-2009-SeiculescuMBM #3d #network #synthesis: SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips (CS, SM, LB, GDM), pp. 9–14.
DAC-2008-JamaaALM #logic #programmable: Programmable logic circuits based on ambipolar CNFET (MHBJ, DA, YL, GDM), pp. 339–340.
DATE-2008-Micheli #design: Designing Micro/Nano Systems for a Safer and Healthier Tomorrow (GDM), p. 1.
DATE-2008-MulasPBCABAM #architecture #multi #policy #streaming: Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures (FM, MP, MB, SC, AA, LB, DA, GDM), pp. 734–739.
DATE-2008-MuraliMAGBBM #manycore #optimisation #using: Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization (SM, AM, DA, RG, SPB, LB, GDM), pp. 110–115.
DATE-2008-RinconPRZSAPM #energy #estimation #framework #network: OS-Based Sensor Node Platform and Energy Estimation Model for Health-Care Wireless Sensor Networks (FJR, MP, JR, QZ, MSE, DA, JP, GDM), pp. 1027–1032.
DATE-2007-AngioliniJABM #design #fault tolerance #interactive: Interactive presentation: Improving the fault tolerance of nanometric PLA designs (FA, MHBJ, DA, LB, GDM), pp. 570–575.
DAC-2006-AtienzaVPPBMM #framework #multi #performance: A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip (DA, PGDV, GP, FP, LB, GDM, JMM), pp. 618–623.
DAC-2006-MuraliABM #fault tolerance #multi #network: A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip (SM, DA, LB, GDM), pp. 845–848.
DATE-2006-MuraliCRGM #multi #network: A methodology for mapping multiple use-cases onto networks on chips (SM, MC, AR, KG, GDM), pp. 118–123.
DATE-2005-GenkoAMMHC #framework: A Complete Network-On-Chip Emulation Framework (NG, DA, GDM, JMM, RH, FC), pp. 246–251.
DATE-2005-MuraliM #design #generative: An Application-Specific Design Methodology for STbus Crossbar Generation (SM, GDM), pp. 1176–1181.
DATE-2005-StergiouACRBM #abstract syntax tree #design #library #network #pipes and filters #synthesis: ast pipes Lite: A Synthesis Oriented Design Library For Networks on Chips (SS, FA, SC, LR, DB, GDM), pp. 1188–1193.
DAC-2004-Micheli #communication #reliability: Reliable communication in systems on chips (GDM), p. 77.
DAC-2004-MuraliM #automation #generative #named: SUNMAP: a tool for automatic topology selection and generation for NoCs (SM, GDM), pp. 914–919.
DATE-v2-2004-JalabertMBM #network: ×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip (AJ, SM, LB, GDM), pp. 884–889.
DATE-v2-2004-MuraliM #architecture: Bandwidth-Constrained Mapping of Cores onto NoC Architectures (SM, GDM), pp. 896–903.
DATE-2003-YeBM #analysis #communication: Packetized On-Chip Interconnect Communication Analysis for MPSoC (TTY, LB, GDM), pp. 10344–10349.
DAC-2002-PeymandoustMS #algebra #embedded #library #using: Complex library mapping for embedded software using symbolic algebra (AP, GDM, TS), pp. 325–330.
DAC-2002-YeMB #analysis #network #power management: Analysis of power consumption on switch fabrics in network routers (TTY, GDM, LB), pp. 524–529.
DATE-2002-BertozziBM #encoding #fault #power management: Low Power Error Resilient Encoding for On-Chip Data Buses (DB, LB, GDM), pp. 102–109.
DATE-2002-MicheliB #design #network #paradigm: Networks on Chip: A New Paradigm for Systems on Chip Design (GDM, LB), pp. 418–419.
DATE-2002-PeymandoustSM #algebra #embedded #optimisation #power management #using: Low Power Embedded Software Optimization Using Symbolic Algebra (AP, TS, GDM), pp. 1052–1058.
DAC-2001-PeymandoustM #algebra #algorithm #synthesis #using: Using Symbolic Algebra in Algorithmic Level DSP Synthesis (AP, GDM), pp. 277–282.
DAC-2001-SimunicBAGM #power management #scalability: Dynamic Voltage Scaling and Power Management for Portable Systems (TS, LB, AA, PWG, GDM), pp. 524–529.
DATE-2001-MartinSZBM #component #design: Component selection and matching for IP-based design (GM, RS, TZ, LB, GDM), pp. 40–46.
DATE-2000-LuCSMB #algorithm #comparison #power management: Quantitative Comparison of Power Management Algorithms (YHL, EYC, TS, GDM, LB), pp. 20–26.
DATE-2000-SemeriaSM #behaviour #c #memory management #pointer #synthesis: Resolution of Dynamic Memory Allocation and Pointers for the Behavioral Synthesis from C (LS, KS, GDM), pp. 312–319.
DATE-2000-SimunicBGM #power management: Dynamic Power Management of Laptop Hard Disk (TS, LB, PWG, GDM), p. 736.
DAC-1999-BeniniMMOP #algorithm #approximate #component #kernel #optimisation: Kernel-Based Power Optimization of RTL Components: Exact and Approximate Extraction Algorithms (LB, GDM, EM, GO, MP), pp. 247–252.
DAC-1999-SimunicBM #embedded #energy #simulation: Cycle-Accurate Simulation of Energy Consumption in Embedded Systems (TS, LB, GDM), pp. 867–872.
DATE-1999-BeniniMMMPS #power management: Glitch Power Minimization by Gate Freezing (LB, GDM, AM, EM, MP, RS), pp. 163–167.
DATE-1999-ChungBBM #power management: Dynamic Power Management for non-stationary service requests (EYC, LB, AB, GDM), pp. 77–81.
DATE-1999-Micheli #c #c++ #hardware #modelling #synthesis: Hardware Synthesis from C/C++ Models (GDM), pp. 382–383.
DATE-1999-SmithM #component #polynomial: Polynomial Methods for Allocating Complex Components (JS, GDM), pp. 217–222.
DAC-1998-BeniniMLMOP #kernel #optimisation: Computational Kernels and their Application to Sequential Power Optimization (LB, GDM, AL, EM, GO, MP), pp. 764–769.
DAC-1998-PaleologoBBM #optimisation #policy #power management: Policy Optimization for Dynamic Power Management (GAP, LB, AB, GDM), pp. 182–187.
DAC-1998-SmithM #automation #component #composition #hardware: Automated Composition of Hardware Components (JS, GDM), pp. 14–19.
DATE-1998-BeniniMSMS #encoding #optimisation: Address Bus Encoding Techniques for System-Level Power Optimization (LB, GDM, DS, EM, CS), pp. 861–866.
DATE-1998-BoglioloBM #behaviour #modelling: Characterization-Free Behavioral Power Modeling (AB, LB, GDM), pp. 767–773.
EDTC-1997-BeniniMMPS #logic #network #optimisation #synthesis: Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks (LB, GDM, EM, MP, RS), pp. 514–520.
EDTC-1997-BoglioloBM #adaptation #behaviour #modelling: Adaptive least mean square behavioral power modeling (AB, LB, GDM), pp. 404–410.
EDAC-1994-YangMD #automaton #constraints #scheduling: Scheduling with Environmental Constraints based on Automata Representations (JCYY, GDM, MD), pp. 495–501.
DAC-1993-DamianiYM #logic #optimisation: Optimization of Combinational Logic Circuits Based on Compatible Gates (MD, JCYY, GDM), pp. 631–636.
DAC-1993-SiegelMD #automation #design: Automatic Technology Mapping for Generalized Fundamental-Mode Asynchronous Designs (PS, GDM, DLD), pp. 61–67.
DAC-1992-DamianiM #equation #logic #optimisation: Recurrence Equations and the Optimization of Synchronous Logic Circuits (MD, GDM), pp. 556–561.
DAC-1992-GuptaCM #component #hardware #simulation #synthesis: Synthesis and Simulation of Digital Systems Containing Interacting Hardware and Software Components (RKG, CJNCJ, GDM), pp. 225–230.
DAC-1991-ErcolaniM #array #programmable: Technology Mapping for Electrically Programmable Gate Arrays (SE, GDM), pp. 234–239.
DAC-1991-KuFM #optimisation: Control Optimization Based on Resynchronization of Operations (DCK, DF, GDM), pp. 366–371.
DAC-1990-KuM #constraints #scheduling: Relative Scheduling Under Timing Constraints (DCK, GDM), pp. 59–64.
DAC-1988-MicheliK #named #synthesis: HERCULES — a System for High-Level Synthesis (GDM, DCK), pp. 483–488.
DAC-1983-MicheliS #array #logic #multi #named #programmable: PLEASURE: a computer program for simple/multiple constrained/unconstrained folding of Programmable Logic Arrays (GDM, ALSV), pp. 530–537.