Travelled to:1 × China
1 × USA
Collaborated with:M.Martonosi A.Bhattacharjee O.Giroux Sameer Sahasrabuddhe Geet Sethi Andrew Wright A.Papakonstantinou Zi Yan D.W.Nellans Caroline Trippel Yatin A. Manerkar M.Pellauer
Talks about:memori (5) model (3) hardwar (2) check (2) gpu (2) multiprocessor (1) comprehens (1) synthesi (1) synchron (1) interfac (1)
Person: Daniel Lustig
DBLP: Lustig:Daniel
Contributed to:
20132011
201620172019Wrote 7 papers:
- HPCA-2013-LustigM #cpu #fine-grained #gpu #latency
- Reducing GPU offload latency via fine-grained CPU-GPU synchronization (DL, MM), pp. 354–365.
- HPCA-2011-BhattacharjeeLM #multi
- Shared last-level TLBs for chip multiprocessors (AB, DL, MM), pp. 62–63.
- ASPLOS-2016-LustigSMB #interface #memory management #named #verification
- COATCheck: Verifying Memory Ordering at the Hardware-OS Interface (DL, GS, MM, AB), pp. 233–247.
- ASPLOS-2017-LustigWPG #automation #memory management #synthesis #testing
- Automated Synthesis of Comprehensive Memory Model Litmus Test Suites (DL, AW, AP, OG), pp. 661–675.
- ASPLOS-2017-TrippelMLPM #hardware #memory management #named #verification
- TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA (CT, YAM, DL, MP, MM), pp. 119–133.
- ASPLOS-2019-LustigSG #analysis #consistency #formal method #memory management
- A Formal Analysis of the NVIDIA PTX Memory Consistency Model (DL, SS, OG), pp. 257–270.
- ASPLOS-2019-YanLNB #memory management
- Nimble Page Management for Tiered Memory Systems (ZY, DL, DWN, AB), pp. 331–345.