Travelled to:4 × USA
Collaborated with:M.Martonosi D.Lustig ∅ Guilherme Cox Zi Yan B.Pichai L.Hsu B.Pham Y.Eckert G.H.Loh Geet Sethi D.W.Nellans Reto Achermann Ashish Panwar T.Roscoe Jayneel Gandhi Mohan Kumar Steffen Maass S.Kashyap Ján Veselý T.Kim T.Krishna
Talks about:translat (5) memori (4) page (4) address (3) multiprocessor (2) architectur (2) manag (2) gpus (2) chip (2) tlb (2)
Person: Abhishek Bhattacharjee
DBLP: Bhattacharjee:Abhishek
Contributed to:
2014
20142011201020162017201820192020Wrote 10 papers:
- ASPLOS-2014-PichaiHB #architecture #cpu #design #memory management
- Architectural support for address translation on GPUs: designing memory management units for CPU/GPUs with unified address spaces (BP, LH, AB), pp. 743–758.
- HPCA-2014-PhamBEL #clustering
- Increasing TLB reach by exploiting clustering in page translations (BP, AB, YE, GHL), pp. 558–567.
- HPCA-2011-BhattacharjeeLM #multi
- Shared last-level TLBs for chip multiprocessors (AB, DL, MM), pp. 62–63.
- ASPLOS-2010-BhattacharjeeM #multi
- Inter-core cooperative TLB for chip multiprocessors (AB, MM), pp. 359–370.
- ASPLOS-2016-LustigSMB #interface #memory management #named #verification
- COATCheck: Verifying Memory Ordering at the Hardware-OS Interface (DL, GS, MM, AB), pp. 233–247.
- ASPLOS-2017-Bhattacharjee
- Translation-Triggered Prefetching (AB), pp. 63–76.
- ASPLOS-2017-CoxB #architecture #multi #performance
- Efficient Address Translation for Architectures with Multiple Page Sizes (GC, AB), pp. 435–448.
- ASPLOS-2018-KumarMKVYKBK #lazy evaluation #named
- LATR: Lazy Translation Coherence (MK, SM, SK, JV, ZY, TK, AB, TK), pp. 651–664.
- ASPLOS-2019-YanLNB #memory management
- Nimble Page Management for Tiered Memory Systems (ZY, DL, DWN, AB), pp. 331–345.
- ASPLOS-2020-AchermannPBRG #named #self
- Mitosis: Transparently Self-Replicating Page-Tables for Large-Memory Machines (RA, AP, AB, TR, JG), pp. 283–300.