Travelled to:2 × USA
Collaborated with:J.S.Emer M.Adler D.Chiou M.A.Kinsy A.Parashar Caroline Trippel Yatin A. Manerkar D.Lustig M.Martonosi Yakun Sophia Shao J.Clemons N.C.Crago Kartik Hegde R.Venkatesan S.W.Keckler C.W.Fletcher
Talks about:hardwar (2) multiplex (1) orchestr (1) multicor (1) explicit (1) trisect (1) softwar (1) problem (1) modular (1) decoupl (1)
Person: Michael Pellauer
DBLP: Pellauer:Michael
Contributed to:
2011
2009
20172019Wrote 4 papers:
- HPCA-2011-PellauerAKPE #manycore #named #simulation #using
- HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing (MP, MA, MAK, AP, JSE), pp. 406–417.
- DAC-2009-PellauerACE #composition #problem
- Soft connections: addressing the hardware-design modularity problem (MP, MA, DC, JSE), pp. 276–281.
- ASPLOS-2017-TrippelMLPM #hardware #memory management #named #verification
- TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA (CT, YAM, DL, MP, MM), pp. 119–133.
- ASPLOS-2019-PellauerSCCHVKF #composition #distributed #named #performance
- Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration (MP, YSS, JC, NCC, KH, RV, SWK, CWF, JSE), pp. 137–151.