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Travelled to:
1 × France
Collaborated with:
L.Sterpone L.Carro S.Wong F.Fakhar
Talks about:
reconfigur (1) techniqu (1) power (1) fpgas (1) clock (1) sram (1) gate (1) base (1) new (1) low (1)

Person: Debora Matos

DBLP DBLP: Matos:Debora

Contributed to:

DATE 20112011

Wrote 1 papers:

DATE-2011-SterponeCMWF #configuration management #power management
A new reconfigurable clock-gating technique for low power SRAM-based FPGAs (LS, LC, DM, SW, FF), pp. 752–757.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.