Travelled to:3 × France
5 × Germany
Collaborated with:M.S.Reorda D.Sabena N.Battezzati F.L.Kastensmidt L.Carro M.Violante F.Abate M.A.Aguirre J.N.Tombs H.Guzmán-Miranda D.Matos S.Wong F.Fakhar L.Cassano D.Cozzi S.Korf J.Hagemeyer M.Porrmann M.Martina G.Masera A.Molino F.Vacca
Talks about:fpgas (5) base (5) new (5) sram (4) test (3) reconfigur (2) algorithm (2) approach (2) effect (2) design (2)
Person: Luca Sterpone
DBLP: Sterpone:Luca
Contributed to:
20132012
2012201120102009200820062005Wrote 9 papers:
- DATE-2013-CassanoCKHPS #configuration management #online #testing
- On-line testing of permanent radiation effects in reconfigurable systems (LC, DC, SK, JH, MP, LS), pp. 717–720.
- DATE-2012-SabenaRS #algorithm #testing
- A new SBST algorithm for testing the register file of VLIW processors (DS, MSR, LS), pp. 412–417.
- PDP-2012-SterponeSR #approach #fault #injection #testing
- A New Fault Injection Approach for Testing Network-on-Chips (LS, DS, MSR), pp. 530–535.
- DATE-2011-SterponeCMWF #configuration management #power management
- A new reconfigurable clock-gating technique for low power SRAM-based FPGAs (LS, LC, DM, SW, FF), pp. 752–757.
- DATE-2010-SterponeB #algorithm #multi
- A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAs (LS, NB), pp. 1231–1236.
- DATE-2009-AbateSVK #case study #functional
- A study of the Single Event Effects impact on functional mapping within Flash-based FPGAs (FA, LS, MV, FLK), pp. 1226–1229.
- DATE-2008-SterponeATG #design #fault tolerance #on the #safety
- On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications (LS, MAA, JNT, HGM), pp. 336–341.
- DATE-DF-2006-MartinaMMVSV #approach #programmable
- A new approach to compress the configuration information of programmable devices (MM, GM, AM, FV, LS, MV), pp. 48–51.
- DATE-2005-KastensmidtSCR #composition #design #logic #on the
- On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs (FLK, LS, LC, MSR), pp. 1290–1295.