Travelled to:1 × China
2 × USA
Collaborated with:Y.Kim O.Mutlu V.Seshadri K.K.Chang J.Liu L.Subramanian G.Pekhimenko S.M.Khan Z.Chishti A.R.Alameldeen C.Wilkerson
Talks about:dram (5) latenc (3) low (2) architectur (1) parallel (1) refresh (1) perform (1) improv (1) common (1) access (1)
Person: Donghyuk Lee
DBLP: Lee:Donghyuk
Contributed to:
201520142013Wrote 3 papers:
- HPCA-2015-LeeKPKSCM #adaptation #optimisation
- Adaptive-latency DRAM: Optimizing DRAM timing for the common-case (DL, YK, GP, SMK, VS, KKWC, OM), pp. 489–501.
- HPCA-2014-ChangLCAWKM #performance
- Improving DRAM performance by parallelizing refreshes with accesses (KKWC, DL, ZC, ARA, CW, YK, OM), pp. 356–367.
- HPCA-2013-LeeKSLSM #architecture #latency #low cost
- Tiered-latency DRAM: A low latency and low cost DRAM architecture (DL, YK, VS, JL, LS, OM), pp. 615–626.