BibSLEIGH corpus
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Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
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Travelled to:
1 × China
3 × USA
Collaborated with:
O.Mutlu D.A.Jiménez A.R.Alameldeen S.M.Khan S.H.Pugsley Z.Chishti S.Lu J.Stark Y.N.Patt J.Kulkarni J.Kim Elvira Teran P.V.Gratz K.K.Chang D.Lee Y.Kim K.A.Bowman J.Tschanz T.Karnik V.De S.Y.Borkar P.Chuang R.L.Scott A.Jaleel K.Chow R.Balasubramonian
Talks about:
perform (3) improv (3) cach (3) processor (2) prefetch (2) program (2) use (2) reconstruct (1) architectur (1) hierarchi (1)

Person: Chris Wilkerson

DBLP DBLP: Wilkerson:Chris

Contributed to:

HPCA 20142014
HPCA 20132013
DAC 20092009
HPCA 20032003
ASPLOS 20172017

Wrote 7 papers:

HPCA-2014-ChangLCAWKM #performance
Improving DRAM performance by parallelizing refreshes with accesses (KKWC, DL, ZC, ARA, CW, YK, OM), pp. 356–367.
HPCA-2014-KhanAWMJ #clustering #performance #using
Improving cache performance using read-write partitioning (SMK, ARA, CW, OM, DAJ), pp. 452–463.
HPCA-2014-PugsleyCWCSJLCB #evaluation #runtime
Sandbox Prefetching: Safe run-time evaluation of aggressive prefetchers (SHP, ZC, CW, PfC, RLS, AJ, SLL, KC, RB), pp. 626–637.
HPCA-2013-KhanAWKJ #architecture #manycore #performance #using
Improving multi-core performance using mixed-cell cache architecture (SMK, ARA, CW, JK, DAJ), pp. 119–130.
Circuit techniques for dynamic variation tolerance (KAB, JT, CW, SLL, TK, VD, SYB), pp. 4–7.
HPCA-2003-MutluSWP #execution #scalability
Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors (OM, JS, CW, YNP), pp. 129–140.
ASPLOS-2017-KimTGJPW #behaviour
Kill the Program Counter: Reconstructing Program Behavior in the Processor Cache Hierarchy (JK, ET, PVG, DAJ, SHP, CW), pp. 737–749.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.