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Travelled to:
1 × China
1 × France
1 × Germany
1 × India
1 × United Kingdom
15 × USA
Collaborated with:
Y.N.Patt H.Kim Y.Kim R.Ausavarungnirun M.A.Suleman Y.Cai E.F.Haratsch K.Mai J.A.Joao C.Wilkerson E.Ebrahimi V.Seshadri C.J.Lee A.K.Mishra C.R.Das D.Lee L.Subramanian S.M.Khan A.R.Alameldeen C.Fallin C.Craik G.Pekhimenko K.K.Chang C.J.Rossbach A.Jog D.Han M.Harchol-Balter M.K.Qureshi B.Grot J.Hestness S.W.Keckler S.Srinath J.Stark S.Ghose Y.Luo D.A.Jiménez R.Das A.Kumar M.Azimi B.Jaiyen R.Agarwal J.Liu M.Besta Syed Minhaj Hassan S.Yalamanchili T.Hoefler T.Huberty R.Cai P.B.Gibbons M.A.Kozuch T.C.Mowry Z.Chishti Amir M. Rahmani Bryan Donyanavard Tiago Mück Kasra Moazzemi A.Jantsch N.D.Dutt Chen Li 0015 Y.Zhang Yang Guo 0003 Jun Yang 0002 M.Kim J.Park Genhee Cho Yoona Kim Lois Orosa J.Kim O.Kayiran N.C.Nachiappan M.T.Kandemir R.Iyer Vance Miller Joshua Landgraf Jayneel Gandhi M.Sadrosadati A.Mirhosseini Seyed Borna Ehsani H.Sarbazi-Azad Mario Drumond B.Falsafi C.Wang H.Cui T.Cao John Zigman Haris Volos 0001 F.Lv X.F.0002 Guoqing Harry Xu Amirali Boroumand Y.Kim Eric Shiu Rahul Thakur D.Kim Aki Kuusela A.Knies P.Ranganathan
Talks about:
memori (12) perform (9) system (8) improv (6) data (6) core (6) prefetch (5) dram (5) effici (4) applic (4)

Person: Onur Mutlu

DBLP DBLP: Mutlu:Onur

Contributed to:

HPCA 20152015
HPCA 20142014
ASPLOS 20132013
DAC 20132013
DATE 20132013
HPCA 20132013
ASPLOS 20122012
DATE 20122012
HPCA 20112011
ISMM 20112011
ASPLOS 20102010
HPCA 20102010
ASPLOS 20092009
HPCA 20092009
ASPLOS 20082008
HPCA 20082008
CGO 20072007
HPCA 20072007
CGO 20062006
HPCA 20032003
PLDI 20192019
ASPLOS 20182018
ASPLOS 20192019
ASPLOS 20202020

Wrote 34 papers:

HPCA-2015-CaiLHMM #memory management #optimisation
Data retention in MLC NAND flash memory: Characterization, optimization, and recovery (YC, YL, EFH, KM, OM), pp. 551–563.
HPCA-2015-LeeKPKSCM #adaptation #optimisation
Adaptive-latency DRAM: Optimizing DRAM timing for the common-case (DL, YK, GP, SMK, VS, KKWC, OM), pp. 489–501.
HPCA-2015-PekhimenkoHCMGK #reuse
Exploiting compressed block size as an indicator of future reuse (GP, TH, RC, OM, PBG, MAK, TCM), pp. 51–63.
HPCA-2014-ChangLCAWKM #performance
Improving DRAM performance by parallelizing refreshes with accesses (KKWC, DL, ZC, ARA, CW, YK, OM), pp. 356–367.
HPCA-2014-KhanAWMJ #clustering #performance #using
Improving cache performance using read-write partitioning (SMK, ARA, CW, OM, DAJ), pp. 452–463.
ASPLOS-2013-JogKNMKMID #array #concurrent #named #owl #performance #scheduling #thread
OWL: cooperative thread array aware scheduling techniques for improving GPGPU performance (AJ, OK, NCN, AKM, MTK, OM, RI, CRD), pp. 395–406.
DAC-2013-MishraMD #approach #design #multi
A heterogeneous multiple network-on-chip design: an application-aware approach (AKM, OM, CRD), p. 10.
DATE-2013-CaiHMM #analysis #memory management #modelling
Threshold voltage distribution in MLC NAND flash memory: characterization, analysis, and modeling (YC, EFH, OM, KM), pp. 1285–1290.
HPCA-2013-DasAMKA #manycore #memory management #policy
Application-to-core mapping policies to reduce memory system interference in multi-core systems (RD, RA, OM, AK, MA), pp. 107–118.
HPCA-2013-LeeKSLSM #architecture #latency #low cost
Tiered-latency DRAM: A low latency and low cost DRAM architecture (DL, YK, VS, JL, LS, OM), pp. 615–626.
HPCA-2013-SubramanianSKJM #in memory #memory management #named #performance #predict
MISE: Providing performance predictability and improving fairness in shared main memory systems (LS, VS, YK, BJ, OM), pp. 639–650.
ASPLOS-2012-JoaoSMP #identification #parallel #scheduling #thread
Bottleneck identification and scheduling in multithreaded applications (JAJ, MAS, OM, YNP), pp. 223–234.
DATE-2012-CaiHMM #analysis #fault #memory management #metric
Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis (YC, EFH, OM, KM), pp. 521–526.
HPCA-2011-FallinCM #named
CHIPPER: A low-complexity bufferless deflection router (CF, CC, OM), pp. 144–155.
ISMM-2011-Mutlu #challenge #manycore #memory management
Memory systems in the many-core era: challenges, opportunities, and solution directions (OM), pp. 77–78.
ASPLOS-2010-EbrahimiLMP #configuration management #manycore #memory management
Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems (EE, CJL, OM, YNP), pp. 335–346.
HPCA-2010-KimHMH #algorithm #memory management #multi #named #scalability #scheduling
ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers (YK, DH, OM, MHB), pp. 1–12.
ASPLOS-2009-SulemanMQP #architecture #execution #manycore #symmetry
Accelerating critical section execution with asymmetric multi-core architectures (MAS, OM, MKQ, YNP), pp. 253–264.
HPCA-2009-EbrahimiMP #data type #hybrid #linked data #open data
Techniques for bandwidth-efficient prefetching of linked data structures in hybrid prefetching systems (EE, OM, YNP), pp. 7–17.
HPCA-2009-GrotHKM
Express Cube Topologies for on-Chip Interconnects (BG, JH, SWK, OM), pp. 163–174.
ASPLOS-2008-JoaoMKAP #object-oriented #performance
Improving the performance of object-oriented languages with dynamic predication of indirect jumps (JAJ, OM, HK, RA, YNP), pp. 80–90.
HPCA-2008-LeeKMP #predict #using
Performance-aware speculation control using wrong path usefulness prediction (CJL, HK, OM, YNP), pp. 39–49.
CGO-2007-KimJMP #compilation
Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors (HK, JAJ, OM, YNP), pp. 367–378.
HPCA-2007-SrinathMKP #feedback #hardware #performance
Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers (SS, OM, HK, YNP), pp. 63–74.
CGO-2006-KimSMP #2d #branch #detection #named #set
2D-Profiling: Detecting Input-Dependent Branches with a Single Input Data Set (HK, MAS, OM, YNP), pp. 159–172.
HPCA-2003-MutluSWP #execution #scalability
Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors (OM, JS, CW, YNP), pp. 129–140.
PLDI-2019-WangCCZVML0X #big data #hybrid #memory management #named
Panthera: holistic memory management for big data processing over hybrid memories (CW, HC, TC, JZ, HV0, OM, FL, XF0, GHX), pp. 347–362.
ASPLOS-2018-Ausavarungnirun #concurrent #gpu #memory management #multi #named
MASK: Redesigning the GPU Memory Hierarchy to Support Multi-Application Concurrency (RA, VM, JL, SG, JG, AJ, CJR, OM), pp. 503–518.
ASPLOS-2018-BestaHYAMH #energy #network #performance #scalability
Slim NoC: A Low-Diameter On-Chip Network Topology for High Energy Efficiency and Scalability (MB, SMH, SY, RA, OM, TH), pp. 43–55.
ASPLOS-2018-BoroumandGKASTK #data flow
Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks (AB, SG, YK, RA, ES, RT, DK, AK, AK, PR, OM), pp. 316–331.
ASPLOS-2018-RahmaniDMMJMD #coordination #manycore #named #resource management
SPECTR: Formal Supervisory Control and Coordination for Many-core Systems Resource Management (AMR, BD, TM, KM, AJ, OM, NDD), pp. 169–183.
ASPLOS-2018-SadrosadatiMESD #hardware #named
LTRF: Enabling High-Capacity Register Files for GPUs via Hardware/Software Cooperative Register Prefetching (MS, AM, SBE, HSA, MD, BF, RA, OM), pp. 489–502.
ASPLOS-2019-0015ARZMGY #framework #memory management
A Framework for Memory Oversubscription Management in Graphics Processing Units (CL0, RA, CJR, YZ, OM, YG0, JY0), pp. 49–63.
ASPLOS-2020-KimPCKOMK #architecture #named #performance
Evanesco: Architectural Support for Efficient Data Sanitization in Modern Flash-Based Storage Systems (MK, JP, GC, YK, LO, OM, JK), pp. 1311–1326.

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