Travelled to:1 × France
1 × Germany
1 × USA
Collaborated with:Y.Liu T.Hwang
Talks about:rail (2) dual (2) architectur (1) methodolog (1) synthesi (1) uniform (1) perform (1) insert (1) fabric (1) driven (1)
Person: Fu-Wei Chen
DBLP: Chen:Fu=Wei
Contributed to:
2012
20092008Wrote 3 papers:
- DAC-2012-ChenH #3d #synthesis
- Clock tree synthesis with methodology of re-use in 3D IC (FWC, TH), pp. 1094–1099.
- DATE-2009-ChenL #design
- Performance-driven dual-rail insertion for chip-level pre-fabricated design (FWC, YYL), pp. 308–311.
- DATE-2008-ChenL #architecture
- Wire Sizing Alternative — An Uniform Dual-rail Routing Architecture (FWC, YYL), pp. 796–799.