BibSLEIGH — TingTing

Travelled to:

5 × Germany
6 × France
7 × USA

Collaborated with:

Y.Liu K.Wang W.Kuo A.C.Wu C.L.Liu A.Hsieh C.Chen H.Chen F.Chen W.Lo K.Chi C.Chang W.Hsieh I.Lin M.Lee S.Huang J.Hwang F.Chiang K.Lin R.M.Owens M.J.Irwin H.Lin Z.Wang A.C.Chang J.Y.Lo K.Kim S.Kang H.Lin C.Chou Y.Hsu M.Chang M.Tsai C.Tseng H.Li

Talks about:

design (9) power (6) synthesi (5) cell (5) low (5) logic (4) architectur (3) engin (3) awar (3) use (3)

Person: TingTing Hwang

DBLP: Hwang:TingTing

Contributed to:

2015

2012

2011

2010

2009

2006

2004

2003

2001

1999

1998

1997

1996

1995

1994

1989

Wrote 21 papers:

DATE-2015-LoCH #architecture #clustering #fault: Architecture of ring-based redundant TSV for clustered faults (WHL, KC, TH), pp. 848–853.
DAC-2012-ChenH #3d #synthesis: Clock tree synthesis with methodology of re-use in 3D IC (FWC, TH), pp. 1094–1099.
DATE-2011-ChenLWH #3d #architecture #network: A new architecture for power network in 3D IC (HTC, HLL, ZCW, TH), pp. 401–406.
DATE-2010-HsiehHCTTL #3d #architecture #design: TSV redundancy: Architecture and design issues in 3D IC (ACH, TH, MTC, MHT, CMT, HCL), pp. 166–171.
DAC-2009-ChenCH #design #information retrieval #order: New spare cell design for IR drop minimization in Engineering Change Order (HTC, CCC, TH), pp. 402–407.
DATE-2009-HsiehH #3d #design #memory management: Thermal-aware memory mapping in 3D designs (ACH, TH), pp. 1361–1366.
DATE-2009-HsiehLH #reduction: A physical-location-aware X-filling method for IR-drop reduction in at-speed scan test (WWH, ISL, TH), pp. 1234–1237.
DATE-2006-LiuH #logic #synthesis: Crosstalk-aware domino logic synthesis (YYL, TH), pp. 1312–1317.
DATE-v1-2004-KuoHW #composition #design #power management: Decomposition of Instruction Decoder for Low Power Design (WAK, TH, ACHW), pp. 664–665.
DATE-v2-2004-LiuWH #logic #synthesis: Crosstalk Minimization in Logic Synthesis for PLA (YYL, KHW, TH), pp. 790–795.
DATE-2003-ChangKWH #named: G-MAC: An Application-Specific MAC/Co-Processor Synthesizer (ACYC, WAK, ACHW, TH), pp. 11134–11135.
DATE-2003-LeeHH #composition #design #finite #power management #state machine: Decomposition of Extended Finite State Machine for Low Power Design (ML, TH, SYH), pp. 11152–11153.
DATE-2003-LoKWH #design #identification #standard: A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs (JYLL, WAK, ACHW, TH), pp. 11102–11103.
DATE-2001-LiuWHL #diagrams: Binary decision diagram with minimum expected path length (YYL, KHW, TH, CLL), pp. 708–712.
DATE-1999-KimKHL #logic #power management #synthesis: Logic Transformation for Low Power Synthesis (KWK, SMK, TH, CLL), pp. 158–162.
DAC-1998-HwangCH #approach #design #power management #re-engineering #using: A Re-engineering Approach to Low Power FPGA Design Using SPFD (JMH, FYC, TH), pp. 722–725.
DAC-1997-ChenHL #approach #design #power management #re-engineering: Low Power FPGA Design — A Re-engineering Approach (CSC, TH, CLL), pp. 656–661.
DAC-1996-ChenLH #layout: Layout Driven Selecting and Chaining of Partial Scan (CSC, KHL, TH), pp. 262–267.
DAC-1995-WangH: Boolean Matching for Incompletely Specified Functions (KHW, TH), pp. 48–53.
EDAC-1994-LinCHH #design: Cell Height Driven Transistor Sizing in a Cell Based Module Design (HRL, CLC, YCH, TH), pp. 425–429.
DAC-1989-HwangOI #communication #complexity #logic #multi #synthesis #using: Multi-Level Logic Synthesis Using Communication Complexity (TH, RMO, MJI), pp. 215–220.